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P r e l i m i n a ry D a t a S h e et , D S 1 , N o v . 2 00 1
SWITI Switching IC
PEF 20451 PEF 20471 PEF 24471 V er s i o n 1 . 3 HTSI HTSI-L HTSI-XL
Wi r ed Communications
Never stop thinking.
Edition 2001-11-16 Published by Infineon Technologies AG, St.-Martin-Strasse 53, D-81541 Munchen, Germany
(c) Infineon Technologies AG 2001.
All Rights Reserved. Attention please! The information herein is given to describe certain components and shall not be considered as warranted characteristics. Terms of delivery and rights to technical change reserved. We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. Infineon Technologies is an approved CECC manufacturer. Information For further information on technology, delivery terms and conditions and prices please contact your nearest Infineon Technologies Office in Germany or our Infineon Technologies Representatives worldwide (see address list). Warnings Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies Office. Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered.
P r e l i m i n a ry D a t a S h e et , D S 1 , N o v . 2 00 1
PEF 20451 PEF 20471 PEF 24471 V er s i o n 1 . 3
Wi r ed Communications
Never stop thinking.
P
R
E
LI
M
IN
HTSI
HTSI-L
HTSI-XL
A
Switching IC
R
SWITI
Y
PEF 20451 / 20471 / 24471 PRELIMINARY Revision History: 2001-11-16 Previous Version: PEF 20451 / 20471 / 24471 V1.2, Preliminary Data Sheet DS1, 2001-04-04 Page 20 35 43 49 68 78 79 83 91 97 112 128 131 144 146 Content Table 6 updated Chapter 3.4.4 updated, added Figure 14 Chapter 3.7.1 and Chapter 3.7.2 updated Chapter 4.3 reworked
DS 1
Description of Configuration Command Register 1 and 2 (CMD1 and CMD2) updated Description of Interrupt Status Register 1 (ISTA1) reworked Description of Interrupt Error Status Register 1 and 2 (IESTA1 and IESTA2) reworked Description of Interrupt Error Mask Register (INTEM2) reworked Description of Source Address (SA) and Destination Address (DA) Registers updated Chapter 6.2 reworked Chapter 6.8.3 reworked Chapter 7.1 and Table 27 "PCM timing" updated Table 28 "PCM Parallel Mode Timing" Table 35 and Figure 57 updated Added Chapter 7.8, "Hardware Reset Timing"
For questions on technology, delivery and prices please contact the Infineon Technologies Offices in Germany or the Infineon Technologies Companies and Representatives worldwide: see our webpage at http://www.infineon.com
PEF 20451 / 20471 / 24471
Table of Contents 1 1.1 1.2 1.3 1.4 1.4.1 1.4.2 1.4.3 1.4.4 2 2.1 2.2 2.2.1 2.2.2 2.2.3 2.2.4 2.2.5 2.2.6 2.2.7 3 3.1 3.2 3.3 3.3.1 3.3.1.1 3.3.1.2 3.3.1.3 3.3.1.4 3.3.1.5 3.3.1.6 3.3.1.7 3.3.2 3.3.3 3.3.4 3.4 3.4.1 3.4.2 3.4.2.1 3.4.2.2 3.4.3 3.4.4 3.4.5
Page
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Overview of Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Features in Detail . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Typical Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Standard PBX or CO Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Computer Telephony Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Router / Remote Access Application . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Voice over IP Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . H-Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Local Bus Interface (PCM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . General Purpose Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clock Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . JTAG Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Microprocessor Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Architectural Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Overview of Functional Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Switching Factory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Switching Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Minimum and Constant Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Subchannel Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Multipoint Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Broadcast Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bidirectional Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Stream-to-Stream Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Message Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Parallel Mode for Local Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Switching Block Error Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Analyze Connection and Data Memory . . . . . . . . . . . . . . . . . . . . . . . . . Clock Generator and PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . General Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Analog PLL (APLL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Jitter-Transfer-Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Master-Slave Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Phase Alignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PLL Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 15 16 16 19 19 20 20 21 22 23 23 24 25 25 25 25 25 26 26 27 29 29 30 30 31 31 32 33 34 35 35 36
Preliminary Data Sheet
2001-11-16
PEF 20451 / 20471 / 24471
Table of Contents 3.4.5.1 3.4.5.2 3.4.6 3.4.7 3.4.7.1 3.4.7.2 3.5 3.6 3.7 3.7.1 3.7.2 4 4.1 4.2 4.2.1 4.2.2 4.2.3 4.2.4 4.2.5 4.3 4.4 4.4.1 4.4.2 4.5 4.6 4.6.1 4.6.2 4.7 4.7.1 4.7.2 4.7.3 4.8 5 5.1 5.2 5.3 5.4 6 6.1 6.2 6.3
Page 36 37 37 37 38 39 42 42 43 43 43 44 44 46 47 47 48 48 48 49 50 50 50 52 53 53 53 54 54 54 55 57 58 59 61 90 91 95 96 97 99
PLL Synchronization H-Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PLL Synchronization M-Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PLL Error Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clock Fallback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clock Signal Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clock Fallback Mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Loops . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Read SWITI Configuration with Indirect Register Addressing . . . . . . . . . . Power-On and Reset Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Hardware Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Software Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Description of Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Local Bus Interface (PCM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . H-Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CT_C8(A/B) and CT_FRAME(A/B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . Dataports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CT_EN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CT_RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . H-MVIP C16 Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Microprocessor Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Intel/Siemens or Motorola Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . De-multiplexed or Multiplexed Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . General Purpose Port (GPIO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . General Purpose Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Frame Group Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GPCLK as Clock Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . JTAG (Boundary Scan) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Boundary Scan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Test-Access-Port (TAP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TAP Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Identification Code via P Read Access . . . . . . . . . . . . . . . . . . . . . . . . . . Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Register Overview For 8-Bit Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . Detailed Register Description For 8-bit Interface . . . . . . . . . . . . . . . . . . . . Register Overview For 16-Bit Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . Detailed Register Description For 16-Bit Interface . . . . . . . . . . . . . . . . . . Programming the Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Read and Write Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupt Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Command and Register Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Preliminary Data Sheet
2001-11-16
PEF 20451 / 20471 / 24471
Table of Contents 6.4 6.5 6.6 6.7 6.8 6.8.1 6.8.2 6.8.3 6.8.3.1 6.8.3.2 6.9 6.9.1 6.10 6.11 6.11.1 6.11.2 6.11.2.1 6.11.2.2 6.11.2.3 6.11.3 6.11.4 6.11.5 6.12 6.13 6.13.1 6.13.2 6.13.3 6.13.4 6.13.5 6.13.6 6.13.7 6.14 7 7.1 7.2 7.3 7.4 7.5 7.6 7.6.1 7.6.2 7.6.3
Page 106 107 108 110 110 110 111 112 112 113 114 114 115 116 116 117 117 118 119 120 121 122 123 124 124 124 124 125 126 126 127 127 128 128 131 132 134 137 138 138 139 142
Indirect Configuration Register Access . . . . . . . . . . . . . . . . . . . . . . . . . . Initialization Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . H.1x0 Clocking Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCM Clocking Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . H.1x0/PCM Line Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Standby Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Determining Clock Rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Performing Bit Shifting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Input Bit Shifting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Output Bit Shifting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Global Clock Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Framing Groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Read Time-Slot Value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Establish Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Establish 8-bit Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Subchannel Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Establish 4-bit Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Establish 2-bit Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Establish 1-bit Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Establish Broadcast Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . Establish Subchannel Broadcast Connection . . . . . . . . . . . . . . . . . . . Establish Multipoint Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Send Messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Release Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Release 8-bit Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Release 4-bit Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Release 2-bit Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Release 1-bit Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Release Broadcast Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Release Subchannel Broadcast Connection . . . . . . . . . . . . . . . . . . . . Release Multipoint Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Stop Sending Messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCM Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCM Parallel Mode Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . H-Bus and PCM (Local Bus) Frame Structure . . . . . . . . . . . . . . . . . . . . . H-Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clock Interoperability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Microprocessor Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Infineon/Intel Timing in De-Multiplexed Mode . . . . . . . . . . . . . . . . . . . Infineon/Intel Timing in Multiplexed Mode . . . . . . . . . . . . . . . . . . . . . . Motorola Microprocessor Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Preliminary Data Sheet
2001-11-16
PEF 20451 / 20471 / 24471
Table of Contents 7.7 7.8 8 8.1 8.2 8.3 8.4 8.5 8.6 9
Page
JTAG Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 Hardware Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Crystal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Capacitances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 147 148 149 150 151 151
Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
Preliminary Data Sheet
2001-11-16
PEF 20451 / 20471 / 24471
List of Figures Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Figure 8 Figure 9 Figure 10 Figure 11 Figure 12 Figure 13 Figure 14 Figure 15 Figure 16 Figure 17 Figure 18 Figure 19 Figure 20 Figure 21 Figure 22 Figure 23 Figure 24 Figure 25 Figure 26 Figure 27 Figure 28 Figure 29 Figure 30 Figure 31 Figure 32 Figure 33 Figure 34 Figure 35 Figure 36 Figure 37 Figure 38 Figure 39 Figure 40 Figure 41 Figure 42 Figure 43
Page
Logic Symbol: HTSI in H-Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Logic Symbol: HTSI in M-Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Standard PBX or CO Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 CT Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Router / Remote Access Applications . . . . . . . . . . . . . . . . . . . . . . . . . 13 Voice over IP Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Bidirectional Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Example for Stream-to-Stream Switching . . . . . . . . . . . . . . . . . . . . . . 29 SWITI Clock Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Block Diagram of APLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 APLL - Jitter Transfer Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Example of Phase Alignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Clock Fallback of Primary Master . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Clock Fallback of Secondary Master . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Clock Fallback of Slave . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 PCM Interface Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 PCM Bit Shifting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 H-Bus Interface in H.100 Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 H-Bus Interface in H.110 Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Multiplexed and in De-multiplexed Bus Mode . . . . . . . . . . . . . . . . . . . 51 GPIO Port Configuration Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Frame Signal Example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Order of Register Access. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 8-bit P Access Interrupt Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 16-bit P Access Interrupt Structure . . . . . . . . . . . . . . . . . . . . . . . . . . 98 Initialization Procedure after Reset . . . . . . . . . . . . . . . . . . . . . . . . . . 107 H.100 Master and Slave Configuration Process . . . . . . . . . . . . . . . . 109 Example: Input Bit Shifting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 Example: Output Bit Shifting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 Example Framing Groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 Example: 8-bit Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 Subchannel Address in Time-Slot . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 Example: 4-bit Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 Example: 2-bit Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 Example: 1-bit Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 Example: Broadcast Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 Example: Subchannel Broadcast Connection . . . . . . . . . . . . . . . . . . 121 Example: Multipoint Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 Example: Send Message . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 PCM Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 Parallel Mode Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
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List of Figures Figure 44 Figure 45 Figure 46 Figure 47 Figure 48 Figure 49 Figure 50 Figure 51 Figure 52 Figure 53 Figure 54 Figure 55 Figure 56 Figure 57 Figure 58 Figure 59 Figure 60 Figure 61
Page 132 133 133 133 134 136 137 139 139 140 141 143 143 145 146 149 151 152
H-Bus and PCM (Local Bus) Clock Alignment . . . . . . . . . . . . . . . . . . H-Bus Frame Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . H.1x0 Detailed Functional Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . H.1x0 Functional Timing for 8, 4 and 2 MBit/s Data Streams . . . . . . Detailed Data Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clock Skew Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SCLK-D Timing for SCbus Operating at 8.192 Mbit/s . . . . . . . . . . . . Infineon/Intel Read Cycle in De-Multiplexed Mode . . . . . . . . . . . . . . Infineon/Intel Write Cycle in De-Multiplexed Mode . . . . . . . . . . . . . . Infineon/Intel Read Cycle in Multiplexed Mode . . . . . . . . . . . . . . . . . Infineon/Intel Write Cycle in Multiplexed Mode . . . . . . . . . . . . . . . . . Motorola Read Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Motorola Write Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Boundary Scan Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Hardware Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . External Crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I/O Wave Form for AC-Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Outlines of P-BGA-217-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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PRELIMINARY Table 1 Table 2 Table 3 Table 4 Table 5 Table 6 Table 7 Table 8 Table 9 Table 10 Table 11 Table 12 Table 13 Table 14 Table 15 Table 16 Table 17 Table 18 Table 19 Table 20 Table 21 Table 22 Table 23 Table 24 Table 25 Table 26 Table 27 Table 28 Table 29 Table 30 Table 31 Table 32 Table 33 Table 34 Table 35 Table 36 Table 37 Table 38 Table 39 Table 40 Table 41 Who should read what? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 SWITI Family Tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 H.100/H.110 Bus Interface (H-mode only) . . . . . . . . . . . . . . . . . . . . . . 16 Local Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 GPIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Clock Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 JTAG Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Microprocessor Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Power Supply Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Stream-to-Stream Connection Mapping . . . . . . . . . . . . . . . . . . . . . . . 28 Data Rates for Local and H-Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Maximum possible data rates for HTSI in M-mode . . . . . . . . . . . . . . . 49 Maximum possible data rates for HTSI in H-mode . . . . . . . . . . . . . . . 49 TAP Controller Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Boundary Scan IDCODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 IDCODE via P Read Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Register Overview For 8-Bit Interface . . . . . . . . . . . . . . . . . . . . . . . . . 59 Value Range for SPA/DPA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Value Range for ITSA/OTSA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Value Range for SCA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Register Overview For 16-Bit Interface . . . . . . . . . . . . . . . . . . . . . . . . 90 Affected Registers for Connection Commands . . . . . . . . . . . . . . . . . . 99 Affected Registers for Configuration Commands. . . . . . . . . . . . . . . . 100 Connection Command and Parameter Codes . . . . . . . . . . . . . . . . . . 102 Configuration Command 1 and Parameter Codes . . . . . . . . . . . . . . . 103 Configuration Command 2 and Parameter Code. . . . . . . . . . . . . . . . 104 PCM Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 PCM Parallel Mode Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 Component Timing Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 Clock Skew Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 SCLK-D Timing at 8.192 Mbit/s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 Infineon/Intel Timing in De-Multiplexed Mode . . . . . . . . . . . . . . . . . . 138 Infineon/Intel Timing in Multiplexed Mode . . . . . . . . . . . . . . . . . . . . . 140 Motorola Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 JTAG Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 Hardware Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 External Capacitances for Crystal (Recommendation) . . . . . . . . . . . 149 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 Input/Output Capacitances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
Preliminary Data Sheet
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PRELIMINARY
Preface
The Switching IC (SWITI) is a family of switching devices for a wide area of telecommunication and data communication applications. This document provides complete reference information according to chip interfaces, programming, internal architecture and applications. Organization of this Document This Preliminary Data Sheet is divided into 9 chapters. It is organized as follows: * Chapter 1, Overview Gives a general description of the product and of the SWITI family, lists the key features, and presents some typical applications. * Chapter 2, Pin Description Lists pin locations with associated signals, categorizes signals according to function, and describes signals. * Chapter 3, Architectural Description Rough overview of the internal architecture and clock fallback feature. * Chapter 4, Description of Interfaces Short introduction of used interfaces. * Chapter 5, Register Description Gives information about all registers accessible via the microprocessor interface according to address, short name, access, reset value and value range. * Chapter 6, Programming the Device Gives a variety of examples how to programm the device, lists all available command and parameter values. * Chapter 7, Timing Diagrams Contains timing diagrams. * Chapter 8, Electrical Characteristics Specification of the electrical parameters. * Chapter 9, Package Outlines Outlines of the available packages (P-BGA-217-1).
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PRELIMINARY Table 1 Programmer Board Designer Related Documentation H.100 Hardware Compatibility Specification: CT Bus, revision 1.0 H.110 Hardware Compatibility Specification: CT Bus, revision 1.0 PCI Specification, revision 2.1, PCI special interest group Compact PCI Specification - PICMG 2.0, revision 2.1 Compact PCI Hot Swap Specification - PICMG 2.1, revision 1.0 H-MVIP Standard, Release 1.1a, GO-MVIP Inc., January 1997 MVIP-90 Standard, Release 1.1, GO-MVIP Inc., October 1994 SC-Bus Specification, ANSI/VITA 6-1994 Who should read what? Relevant Chapters 3, 5, 6 2, 3, 4, 7, 8, 9
Addressed Person
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PRELIMINARY Overview
1
Overview
The new switching family, called SWITI, provides a complete and cost-effective solution for all switching systems. The family is divided in two sub-families, the MTSI family and the HTSI family. The Preliminary Data Sheet describes the functionality and characteristic of the HTSI devices. The devices can be used in today's switching applications, e.g. conventional PBXs and central offices (CO's), as well as in H.100/H.110 applications (only the HTSI family), which are the key to high performing CTI- and Voice-over-IP-applications, one of the most important future technologies in telecommunications. The main requirements of today's switching applications are met by the following features: * Constant delay e.g. to support wide band data switching, or channel bundling * Bit switching/subchannel switching to support applications such as mobile base stations, DECT, computer telephony In addition, the SWITI family provides new features to ensure a broad range of configurations to make it possible to adapt the device to all switching applications: * * * * A compliant H.100/H.110 interface (HTSI) 8-channel stream-to-stream switching capability (HTSI) Message mode, which allows to assign a preset value to any output time-slot GPIO (General Purpose I/O) port, which is controlled from the external P
SWITI family. The SWITI family consists of 6 ICs with different switching capacities. The possible configurations are shown in Table 2. The HTSI versions provide an additional H.100 / H.110 interface, while the MTSIs are standard switching devices. All devices can be programmed easily, thus helping the designer/programmer to integrate the device into his application comfortably. Table 2 Name HTSI-XL (H-Mode) HTSI-XL (M-Mode) HTSI-L (H-Mode) HTSI-L (M-Mode) P-BGA-217-1 SWITI Family Tree Package P-BGA-217-1 Sales code PEF 24471 HTSI-XL PEF 24471 HTSI-XL PEF 20471 HTSI-L PEF 20471 HTSI-L 1024 Connections 2048 Local bus IN/OUT 16/16 32/32 16/16 32/32 H-Bus I/O 32 32 -
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PRELIMINARY Table 2 Name HTSI (H-Mode) HTSI (M-Mode) MTSI-XL MTSI-L MTSI SWITI Family Tree (cont'd) Package P-BGA-217-1 Sales code PEF 20451 HTSI PEF 20451 HTSI P-MQFP-100-2 PEF 24470 MTSI-XL P-MQFP-100-2 PEF 20470 MTSI-L P-MQFP-100-2 PEF 20450 MTSI 2048 1024 512 Connections 512 Local bus IN/OUT 16/16 32/32 16/16 16/16 16/16 H-Bus I/O 32 Overview
HTSI devices. The HTSI devices can be operated in two different modes, H-Mode and M-Mode. In H-Mode the device offers 16 local I/Os and additionally a compliant H.100/H.110 interface (32 bidirectional I/Os). The complete number of available connections can be assigned as H-bus to H-bus, local bus to local bus connection, or mixed. In M-Mode all lines are configured as local I/Os, so that in total 32 local I/Os are provided. Thus e.g. the HTSI-XL device can be used as 2K non-blocking switch operating with all 32 I/Os at 4.096 Mbit/s.
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PRELIMINARY
Switching IC SWITI
PEF 20451 / 20471 / 24471
Version 1.3
CMOS
1.1
General
Overview of Features
* Switching capacity of 512, 1024, or up to 2048 connections of different types between different buses * Programmable data rates of 2.048 Mbit/s, 4.096 Mbit/s, 8.192 Mbit/s, and 16.384 Mbit/s on per P-BGA-217-1 stream basis * Constant delay or minimum delay programmable on per connection basis * Subchannel switching ability of 1-bit, 2-bit, 4-bit wide time-slots * Programmable clock shift for local bus * 8-channel stream-to-stream switching for H.100/H.110 and interoperability bus * Automatic data rate adaption * Optional 8-bit parallel input and/or 8-bit parallel output for first 8 lines of local bus * Broadcast capabilities * Multipoint switching ability * Read and write access to all time-slots * Message mode (time-slot write access) * Programmable framing group * GPIO port * 8-bit P-interface supports both Intel and Motorola mode * Optional 16-bit P interface mode (instead of GPIO port) * On chip PLL for H.100/H.110, SCbus, MVIP, MVIP-H clock operation (master/slave) and for local bus clock operation (master/slave) * JTAG interface - Boundary scan according to IEEE 1149.1 * 3.3 V power supply * 5 V tolerant inputs/outputs
Type PEF 20451 / 20471 / 24471
Preliminary Data Sheet 5
Package P-BGA-217-1
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PRELIMINARY HTSI in H-Mode * H.100/H.110 compliant interface with all mandatory signals * Local bus of up to 16 PCM ports (16 In/16 Out) * Hot swapping HTSI in M-Mode * Local bus of up to 32 PCM ports (32 In/32 Out). Overview
1.2
Features in Detail
Flexible Data Rates Each input and each output line of the local bus is programmable to operate at different data rates. The possible data rates are 2.048 Mbit/s, 4.096 Mbit/s, 8.192 Mbit/s, and 16.384 Mbit/s. Even for the HTSI in M-Mode all of the 32 input lines and 32 output lines are configureable, except for the bit rate of 16.384 Mbit/s. In case of 16.384 Mbit/s only 24 lines can be used. The possible data rate for the data lines of the H-Bus are 2.048 Mbit/s, 4.096 Mbit/s and 8.192 Mbit/s. Constant and Minimum Delay Each connection independent of the addressed buses can be determined to be a constant delay or minimum delay connection. Constant delay means that any input timeslot or subchannel is available on the programmed output after 2 frames. Minimum delay means that the time-slot or subchannel appears at the output as soon as possible. The minimum delay depends on the chosen connections and the possible range is between 0 and 2 frames. Subchannel Switching Each connection can be a 1-bit, 2-bit, 4-bit, or 8-bit connection. Subchannel switching is applicable to both the local bus and the H-Bus and has a constant delay of 2 frames. Sub-Channel switching is supported only for data rate of 2.048 Mbit/s, 4.096 Mbit/s and 8.192 Mbit/s. Programmable Clock Shift The position of time-slot 0 of each local bus input line can be programmed within the time-slot before and after the PFS rising edge in half clock steps. Also the position of time-slot 0 of all local bus output lines can be programmed within the first time-slot after the PFS rising edge.
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PRELIMINARY 8-Channel Stream-to-Stream Switching This feature offers the possibility to efficiently switch one data stream to another at the same or different data rates without occupying switching memory capacity. It mainly supports interoperability between CT-bus (Computer Telephony) devices such as SCbus and MVIP-90 running at different data rates. It is possible to use up to 8 lines from the H.1x0 data lines to establish the connections. Input and output frequency can be configured differently. Automatic Data Rate Adaption Connections are also possible between lines operating at different data rates. The programmer just specifies input and output line, time-slot, and if necessary, the subchannel. Parallel Mode The first 8 local bus input and output lines can be configured to one parallel input or output port respectively. In serial mode a time-slot is determined by 8 consecutive data clock cycles according to each line. In parallel mode a time-slot is determined by 1 data clock cycle according to the first 8 lines. Broadcast With this feature it is possible to distribute one incoming time-slot to different output timeslots. Multipoint Multipoint connections can be seen as the opposite of broadcast connections. Here it is possible to generate one output time-slot consisting of several input time-slots. The specified input time-slots are logically AND or OR connected (selectable) and have a constant delay of 2 frames. Read Access The programmer has access to any input time-slot. After issuing an appropriate command the arrival of the time-slot will be reported by interrupt. The value can be read from a dedicated register. For every read request the command has to be issued again. Message Mode (Write Access) This feature allows a constant value to be sent to any given output time-slot. Overview
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PRELIMINARY Framing Group It is possible to specify up to 8 different framing signals of 8 kHz. The position of the rising edge and the pulse width can be programmed for each signal. The reference frame is determined by the PFS signal. The pulse parameters are programmed in half step resolution according to a 16.384 MHz clock. General Purpose Clocks All 8 GPCLK lines can be configured as individual clock outputs with 8 kHz, 2.048 MHz, 4.096 MHz, 8.192 MHz, 16.384 MHz and for test purposes with the internal frequency or the input frequency of the analog PLL (APLL). GPIO Port Each line of the general purpose input/output port can be configured to be either input or output. According to an input an edge causes an interrupt. The outputs can be influenced by write access via the microprocessor interface. Thus the user has the possibility to observe and influence additional signals for his application. Microprocessor Interface All devices provide a standard 8-bit microprocessor interface operating in either Intel or Motorola mode. Optionally it is possible to configure the GPIO port as additional data lines to provide a 16-bit microprocessor interface. The use of the 16-bit P interface reduces the number of write cycles required to configure a connection from 7 (in case of 8-bit P interface) to 3 write cycles. Input/Output Tolerance The HTSI can be used in a 5 V environment with two additional 5 V (VDD) power supply pins. Local input and outputs are 3.3 V and 5 V tolerant. The outputs have TTL level driving capability. The H-Bus lines of the HTSI can be used in a 3.3 V signaling PCI environment. Overview
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PRELIMINARY Overview
1.3
Logic Symbol
The HTSI is dedicated to perform time-slot switching between the local bus and the HBus or to offer a solution for applications with a high number of local I/Os. The HTSI operates in two modes. In H-Mode (Figure 1) it works with the H-Bus and in M-Mode (Figure 2) it operates without the H-Bus. The HTSI in H-Mode provides 16 PCM input lines and 16 PCM output lines and the complete H-Bus with 32 bidirectional H.100/H.110 data lines.
VDD VSS
IN[15:0] OUT[15:0] PFS PDC
CT_D[31:0] /CT_FRAME_A CT_C8_A /CT_FRAME_B CT_C8_B
General Purpose Clocks
CT_NETREF(_1) CT_NETREF_2
GPIO
HTSI PEF 20451/20471/24471
/CT_EN /CT_RESET /FR_COMP SCLK
Misc.
TRST TCK TMS TDI TDO
SCLKx2* / SCLK-D C2 /C4 /C16+ /C16-
D[7:0]
A[4:0]
RD DS
WR R/W
CS
IREQ IREQ
RESET
ALE
MODE16
switi_002.emf
Figure 1
Logic Symbol: HTSI in H-Mode
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PRELIMINARY Overview
If no H-Bus is needed it is possible to configure the HTSI in M-Mode. In this mode, the HTSI provides 32 PCM input lines and 32 PCM output lines.
VDD
VSS
IN[31:0] PFS PDC
OUT[31:0]
TRST TCK TMS TDI TDO
HTSI PEF 20451/20471/24471
General Purpose Clocks
GPIO
Misc.
D[7:0]
A[4:0]
RD DS
WR R/W
CS
IREQ IREQ
RESET
ALE MODE16
switi_003.emf
Figure 2
Logic Symbol: HTSI in M-Mode
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PRELIMINARY Overview
1.4
Typical Applications
Typical applications of the SWITI family are: * PCM switch, concentrator or multiplexer in PBXs, COs or mobile base stations * H.100/H.110 interface in - Computer telephony systems - Internet telephony systems - LAN/WAN access devices - Enhanced service platforms The following sections give a general overview of the system integration of the SWITI family.
1.4.1
Standard PBX or CO Application
The MTSI or the HTSI in M-Mode can be used, just as the MTSC or MTSL, in standard private branch exchange or central office applications (Figure 3), e.g. in the switching network.
PBX or CO Line Unit EPIC/ DELIC PCM Switching Network MTSI/ HTSI
PCM SLMD Subscriber Line Modul Digital EPIC/ DELIC PCM MTSI/ HTSI HDLC
Coordination Processor CP
switi_014.emf
Figure 3
Standard PBX or CO Application
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PRELIMINARY Overview
1.4.2
Computer Telephony Application
In Computer Telephony Integration (CTI) applications, resources such as the analog telephone line cards, ISDN ports, switching controllers, FAX firmware, or voice processing modules are in the form of plug-in cards that sit on the ISA or PCI slots of a PC. Resource sharing is established by connecting the top of the plug-in cards with cables. This Time Division Multiplex (TDM) bus has evolved from the original H-MVIP, MVIP-90, Dialogic's SC-Bus, into the latest H.100/H.110 bus or H-Bus developed by the Enterprise Computer Telephony Forum (ECTF). By connecting to the H.100/H.110 interface devices, system modules may send and receive data to and from any one of the 4096 TDM time-slots of the H-Bus. The H-Bus also offers the ideal solution for routers to provide a bridge between the data communication and telecommunication system modules. In Computer Telephony (CT) environment, resource sharing is accomplished by passing data back and forth through the H.100/H.110 bus. Figure 4 shows the example.
H.100/H.110
HTSI
HTSI
HTSI
HTSI
Base Transceiver Station (BTS)
Line Cards
DSP
Voice Recognition
switi_010.emf
Figure 4
CT Application
Preliminary Data Sheet
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PRELIMINARY Overview
1.4.3
Router / Remote Access Application
The HTSI (H-Mode) or also the MTSI (if no H-Bus interface is used in the system) is used in multivoice applications as the bridge connecting the data communication modules to the telecommunication modules in a router/remote access design. Figure 5 shows the example.
H.100/H.110
PCM/IOM-2 FALC54 (Framer)
LAN
HTSI
CODEC Server HTSI HTSI MUNICH32 (HDLC)
Modem Pool
HTSI
LAN
switi_009.emf
Figure 5
Router / Remote Access Applications
Preliminary Data Sheet
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PRELIMINARY Overview
1.4.4
Voice over IP Application
In a voice over IP application (Figure 6) the HTSI (in H-Mode) may be used to connect a conventional PBX to the H-Bus. A Vocoder card, also connected to the H-Bus, performs speech compression and decompression whereas an Ethernet card transmits and receives the compressed data over the network.
H.100/ H.110 HTSI HTSI Vocoder
PCI/cPCI
PCM
Processor
PBX
Ethernet
E1/T1
LAN/WAN
switi_004.emf
Figure 6
Voice over IP Application
Preliminary Data Sheet
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PRELIMINARY Pin Description
2
Pin Description
The pin description gives an overview of the pin numbers, names, direction, position and function ordered by the different interfaces. Note: All unused input or I/O pins should be connected to VSS to avoid leakage current.
2.1
Pin Diagram
P-BGA-217-1
17
NC NC GPCLK_2 VDD
16
NC VSS NC
15
CT_D_0 /IN_16 VDD VSS
14
CT_D_2/ IN_18 IN_1 VSS
13
IN_3 VDD5 IN_2 IN_0
12
IN_5
11
VSS
10
9
8
CT_D_8/ IN_24 VDD5 VSS VDD
7
IN_9 CT_D_9 /IN_25
6
5
VDD
4
3
2
NC VSS VDD C2 A_2 VSS D_0 D_3 VDD /FR_ COMP GPIO_0 VSS
1
NC NC WR R/W A_1 VDD /C16+ D_2 /C16VSS D_5 D_7 VDD
CT_D_6/ CT_D_7/ IN_22 IN_23 IN_7 IN_8 VSS
IN_11
CT_D_12 CT_D_14/ /IN_28 IN_30 IN_14 NC
A B C D E F G H J K L M N P R
T
CT_D_3/ CT_D_5/ IN_21 IN_6 IN_19 VSS IN_4 VDD VDD
CT_D_11 IN_12 /IN_27
CT_D_10 /IN_26 VSS IN_10 IN_13
CT_D_13 CT_D_15/ VSS /IN_29 IN_31 IN_15 VSS RD/DS ALE A_4 VSS A_0 /C4 A_3 D_1 D_4 D_6 SCLK GPIO_3 GPIO_6 VSS VSS
/CT_ FRAME_A GPCLK_0 VSS GPCLK_3 GPCLK_1
CT_D_1/ CT_D_4/ IN_20 IN_17
GPCLK_5 VSS
GPCLK_7 GPCLK_6 CT_C8_A GPCLK_4 VSSA VDDA /CT_ FRAME_B CT_C8_B
P-BGA- 217-1
VSS VSS VSS VSS VSS VSS VSS VSS VSS
ECLKO ECLKI H110MODE
CT_ M-MODE NETREF2 VDD RESERV. RESERV. VSS /CT_ RESET NTW K_2 RESET VDD PFS TMS VSS NC OUT_0 VDD IREQ CT_ NETREF1 TDO VSS VDD VSS OUT_1 CT_D_17/ CT_D20/ OUT_17 OUT20 VDD5 OUT_4 OUT_5
VDD VSS VDD GPIO_1
NTW K_1 VDD VSS CS PDC TDI NC NC MODE16 VSS TRST TCK VSS NC
Bottom View
VDD VDD VSS VSS VDD OUT_10 CT_D_26 /OUT_26 OUT_9 OUT_13 VDD OUT_11 CT_D22/ OUT22 VSS CT_D_23 CT_D_24 /OUT_23 /OUT_24 OUT_7 OUT_8
GPIO_5 VDD CT_D_30/ OUT_30 VSS CT_D_28/ OUT_28 OUT_15 VSS
SCLKx2* SCLK-D GPIO_2 GPIO_7 GPIO_4
NC
/CT_EN NC NC switi_076.em f
CT_D_16/ CT_D_18/ OUT_16 OUT_18 OUT_3 OUT_2 VSS
CT_D_29/ CT_D_31 OUT_29 /OUT_31 VSS NC
CT_D_19/ CT_D_21 OUT_19 /OUT_21 OUT_6
VDD5
CT_D_25/ CT_D_27/ OUT_25 OUT_27 OUT_12 OUT_14
U
Figure 7
Pin Configuration
Preliminary Data Sheet
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PRELIMINARY Pin Description
2.2 2.2.1
Pin Definitions and Functions H-Bus Interface
The following table (Table 3) is only applicable for the H-mode except the CT_D (IN/ OUT) lines. Table 3
Pin No. D16
H.100/H.110 Bus Interface (H-mode only)
Symbol CT_FRAME_A In (I) Function Out (O) I/O H.1x0 only Frame Sync - driven by the "A" clock master. This is a negative true pulse, nominally 122 ns wide that straddles the beginning of the first bit of the first time slot. It has a period of 125 s. H.1x0 only Bit Clock - driven by "A" clock master. The clock frequency is 8.192 MHz. The duty cycle of this signal is nominally 50%. H.1x0 only Redundant Frame Sync - driven by the "B" clock master. This is a negative true pulse, nominally 122 ns wide that straddles the beginning of the first bit of the first time slot. It has a period of 125 s. H.1x0 only Redundant Bit Clock - driven by "B" clock master. The clock frequency is 8.192 MHz. The duty cycle of this signal is nominally 50%. H-Mode Serial Data lines that can be driven by any board in the system. However, only one board can drive the bus at any given time slot on each stream. Each signal contains 128 time slots per frame at a clock frequency of 8.192 MHz. These 32 signals collectively are referred to as the CT_D bus. CT Bus devices may connect to subsets of the CT_D bus. Reset Behavior High Z
F15
CT_C8_A
I/O
High Z
G15
CT_FRAME_B
I/O
High Z
G14
CT_C8_B
I/O
High Z
T3, P5, T4, R5, U5, R7, U6, T8, T9, R9, U11, P11, U12, T13, P12, T14, C4, A3, C5, A4, B6, C7, B7, A8, A9, A10, B11, D11, B12, A14, D12, A15
CT_D[31:0]1)
I/O
High Z
CT_D[15:0] as IN[31:16] CT_D[31:16] as OUT[31:16]
I
M-mode PCM Receive Data Port 16 to 31 (PCM mode only)
O
PCM Transmit Data Port 16 to 31 (PCM mode only)
High Z
Preliminary Data Sheet
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PRELIMINARY Table 3
Pin No. M14
Pin Description
H.100/H.110 Bus Interface (H-mode only) (cont'd)
Symbol CT_NETREF_1 In (I) Function Out (O) I/O H.1x0 Additional Network Timing Reference - driven by any (single) CT Bus digital trunk interface to provide network synchronization to the CT Bus. This signal can have any duty cycle as long as the period is 125 s (8 kHz), 647 ns (1.544 MHz), or 488 ns (2.048 MHz) and is network synchronized. There is no specified phase relation to CT_NETREF_2 and the other clocks. It has a minimum high of 90 ns and a minimum low time of 90 ns. H.1x0 Additional Network Timing Reference - driven by any (single) CT Bus digital trunk interface to provide network synchronization to the CT Bus. This signal can have any duty cycle as long as the period is 125 S (8 kHz), 647 ns (1.544 MHz), or 488 ns (2.048 MHz) and is network synchronized. There is no specified phase relation to CT_NETREF_1 and the other clocks. It has a minimum high time of 90 ns and a minimum low time of 90 ns. H.110 only Logic low signal to indicate that J4 of a CT Bus card is fully seated. H.110 only Logic low signal used to reset all CT Bus cards that do not have access to the PCI RST# reset from J1/P1. H.1x0 Compatibility frame pulse - driven by current clock master. This is a negative true pulse, nominally 122 ns wide, that straddles the beginning of the first bit of the first time slot. It has a period of 125 s. This signal serves as the frame synchronization signal for SCbus (Fsync*) and MVIP (/F0). H.1x0 SCbus System clock - driven by current clock master. The clock is selectable. It can be either 2.048 MHz, 4.096 MHz, or 8.192 MHz. It is used to identify the data bit positions on the SCbus. The positive going edge indicates the beginning of the bit. H.100 SCbus System (SCLK) clock times two - driven by current clock master. The clock frequency is exactly twice that of SCLK. Transitions of SCLK occur on the falling edge of SCLKx2* for SCbus operating at 2.048 MHz, 4.096 MHz, or 8.192 MHz. H.110 Inter-operability clock - driven by current clock master. The clock frequency is 8.192 Mhz. It is used to identify the data bit positions on the ANSI VITA 6, SCbus. The positive going edge indicates the sample point of the bit. High Z Reset Behavior High Z
H15
CT_NETREF_2
I/O
High Z
R1
CT_EN
I
K16
CT_RESET
I
K2
FR_COMP
I/O
L3
SCLK
I/O
High Z
N2
SCLKx2*
I/O
High Z
SCLK-D
Preliminary Data Sheet
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PRELIMINARY Table 3
Pin No. D2
Pin Description
H.100/H.110 Bus Interface (H-mode only) (cont'd)
Symbol C2 In (I) Function Out (O) I/O H.1x0 MVIP-90 bit clock - driven by current clock master. The clock frequency is 2.048 MHz, nominally symmetrical. The positive going edge indicates the beginning of the bit. H.1x0 MVIP-90 bit clock times two - driven current by clock master. The clock frequency is exactly twice C2, and transitions of C2 are synchronous with the falling edge of C4. H.1x0 H-MVIP 16.384 MHz Positive active low Clock. High to low transition on frame boundary H.1x0 H-MVIP 16.384 MHz Negative active low Clock. Low to high transition on frame boundary Mode Selection Pin for H-Mode or M-Mode low=H-Bus is in normal H.100/H.110 mode (H-Mode) high=H-Bus interface is additional PCM interface (port 16 to 31), (M-mode) Mode Selection Pin for H.100/H.110 low = the H-Bus operates in H.100 mode high = the H-Bus operates in H.110 mode Note: The pin must be connected to VSS in MMODE Reset Behavior High Z
F3
C4
I/O
High Z
F1
C16+
I/O
High Z
H1
C16-
I/O
High Z
H16
M-MODE2)
I
K17
H110-MODE3)
I
1) 2) 3)
T3 is CT_D31, P5 is CT_D30, T4 is CT_D29.. Pin has to be connected to VDD or VSS as required. The pin information is sampled during reset. Pin has to be connected to VDD or VSS as required The pin information is sampled during reset. The pin must be connected to VSS in M-MODE.
Preliminary Data Sheet
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PRELIMINARY Pin Description
2.2.2
Table 4
Pin No. N15 P17 D5, B4, D6, B5, A6, D7, A7, C9, B9, B10, A12, C11, A13, C13, B14, D13 R4, U3, P6, U4, T6, P7, T7, U8, U9, U10, T11, R11, T12, U14, R13, U15
1) 2)
Local Bus Interface (PCM)
Local Bus Interface
Symbol PFS PDC IN[15:0]1) In (I) Function Out (O) I/O I/O I PCM Frame Synchronization Clock of 8 kHz PCM Data Clock of 2.048 Mbit/s, 4.096 Mbit/s, 8.192 Mbit/s, 16.384 Mbit/s PCM Receive Data Port 15 to 0 Reset Behavior High Z High Z
OUT[15:0]2)
O
PCM Transmit Data Port 15 to 0
High Z
D5 is IN15, B4 is IN14, D6 is IN13.. R4 is OUT15, U3 is OUT14, P6 is OUT13..
2.2.3
Table 5
Pin No. P2, N3, M4, P1, M3, N1, L4, L2
1)
General Purpose Port
GPIO
Symbol GPIO[7:0]1) In (I) Function Out (O) I/O Reset Behavior
General Purpose I/O port (only if 8-bit P interface used) Input
D[15:8]
Upper 8 bit of 16-bit P interface
P2 is GPIO7, N3 is GPIO6, M4 is GPIO5..
Preliminary Data Sheet
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PRELIMINARY Pin Description
2.2.4
Table 6
Pin No. J17 H17
Clock Signals
Clock Pins
Symbol ECLKI ECLKO
1)
In (I) Function Out (O) I O O External Crystal Input of 16.384 MHz, or 32.768 MHz External Oscillator Input of 16.384 MHz, or 32.768 MHz External Crystal Output of 16.384 MHz, or 32.768 MHz General Purpose Clock Output (Framing Signals)
Reset Behavior
F17, F16, GPCLK[7:0] E17, F14, E15, C17, E14, D15 L17 NTWK_1
High Z
I
Primary Network Timing Reference Input Optionally the PLL can be synchronized to this input which can be 8 kHz, 512 kHz, 1.536 MHz, 1.544 MHz, 2.048 MHz Secondary Network Timing Reference Input Optionally the PLL can be synchronized to this input which can be 8 kHz, 512 kHz, 1.536 MHz, 1.544 MHz, 2.048 MHz
K15
NTWK_2
I
1)
F17 is GPCLK7, F16 is GPCLK6, E17 is GPCLK5..
2.2.5
Table 7
Pin No. R16 P15
JTAG Interface
JTAG Interface
Symbol TCK TMS In (I) Out (O) I I Function Test Clock Single rate test data clock. Test Mode Select A '0' to '1' transition on this pin is required to step through the TAP controller state machine. Test Reset Resets the TAP controller state machine (asynchronous reset). Test Data Out In the appropriate TAP controller state test data or a instruction is shifted out via this line. Test Data Input In the appropriate TAP controller state test data or a instruction is shifted in via this line. High Z Reset Behavior
P16
TRST
I
N14
TDO
O
R17
TDI
I
Preliminary Data Sheet
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PRELIMINARY Pin Description
2.2.6
Table 8
Pin No. N17
Microprocessor Interface
Microprocessor Interface
Symbol CS In (I) Out (O) I Function Chip Select Active low. A "low" on this line selects all registers for read/ write operations. Read (Intel/Infineon Mode) Indicates a read access. Data Strobe (Motorola Mode) During a read cycle, DS indicates that the device should place valid data on the bus. During a write access, DS indicates that valid data is on the bus. I Write (Intel/Infineon Mode) Indicates a write access. Read/Write (Motorola Mode) Indicates the direction of the data transfer on the bus. I Address Latch Enable Controls the on-chip address latch in multiplexed bus mode. While ALE is 'high', the latch is transparent. The falling edge latches the current address. ALE is also evaluated to determine the bus mode (ALE fix 'low' = Motorola, fix 'high' = Intel/Infineon) Microprocessor Bus 8/16-Bit Interface Selection ('low' = 8 bit, 'high' = 16 bit) Interrupt Request This pin is programmable to push/pull (active high or low) or open-drain. This signal is activated when SWITI requests an P interrupt. When operated in open drain mode, multiple interrupt sources may be connected. Address Bus When operated in address/data multiplex mode, the address pins are externally connected to the D bus. Data bus Input High Z Reset Behavior
E4
RD
I
DS
C1
WR
R/W F4 ALE
M16 L14
MODE16 IREQ/ IREQ
I O OD
G4, G3, E2, D1, E3 L1, K3, K1, J3, H2, G1, H3, G2 L15
1) 2)
A[4:0]1)
I
D[7:0]2)
I/O
RESET
I
System Reset SWITI is forced to go into reset state.
G4 is A4, G3 is A3, E2 is A2.. L1 is D7, K3 is D6, K1 is D5..
Preliminary Data Sheet
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PRELIMINARY Pin Description
2.2.7
Table 9
Pin No.
Power Supply
Power Supply Pins
Symbol VDD I In (I) Out (O) Function Power Supply 3.3 V
C2, E1, J2, M1, N4, R6, R10, R14, M15, D17, B15, C10, A5, D8, D10, H4, H14, K4, P8, P10, K14, L16 B8, B13, R12, U7
VDD5
I
I/O Reference Voltage 5,0 V for 5 V tolerant I/Os. Pins must be connected at 3,3 V in a 3,3 V signal environment Digital Ground (0 V)
D3, F2, J1, M2, P3, T5, R8,T10, U13, P13, N16, M17, E16, C14, C12, A11, C8, C6, B2, B16, C3, C15, D4, D9, D14, H8, H9, H10, J4, J8, J9, J10, J14, K8, K9, K10, P4, P9, P14, R3, R15, T2, T16 G16 G17 J16 J15 B1, R2, U2,T15, T17, C16, A16, B3, A1, T1, U1, U16, U17, B17, A17, A2
VSS
I
VDDA VSSA R R NC
I I
Power Supply Analog Logic 3.3 V Used for PLL Analog Ground (0 V) Reserved. Must be connected to VSS Reserved. Must be connected to VSS Not Connected
Preliminary Data Sheet
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PRELIMINARY Architectural Description
3
Architectural Description
The following sections give a short overview of the functionality of the SWITI.
3.1
Functional Block Diagram
P ro g ra m m in g
G P IO s
JT A G
P -In te rfa ce
PLL
C lo cks
Sw itching Factory
C o n sta n t D e la y / S u b ch a n n e l
Line, TS In p u t H a n d le r
C o n tro l
In p u t D a ta M e m o ry
C o n tro l
L in e , T S O u tp u t H a n d le r
C o n tro l
O u tp u t D a ta M e m o ry
M in im u m D e la y
L o ca l B u s
I/O B lo ck w . A u to m a tic D a ta R a te A d a p tio n
H .1 x0 B u s
L o ca l I/O s
H .1 x0 I/O s
sw iti_ 0 7 8 .e m f
Figure 8
Block Diagram
23 2001-11-16
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PRELIMINARY Architectural Description
3.2
Overview of Functional Blocks
Switching Factory The switching factory is responsible for transferring and handling the incoming data streams to the assigned output channels and time-slots. The block includes a 512, 1024, or 2048 byte input and output data memory as far as an input and output connection memory. Local bus and H-Bus I/O Block The block is designed to handle the conversion of the data provided via the switching block and the external PCM and H.1x0 interface. It performs the PCM and H.1x0 timing, the data rate selection and the tristate control. Microprocessor Interface Block A standard 8-bit multiplexed or de-multiplexed P interface is provided, compatible to Intel/Infineon Tech. (e.g. 80386EX, C166) and Motorola (e.g. 68040, 68340, 68360, 801) bus systems. If the GPIO port is not needed it can be used to provide a 16-bit P interface. GPIO Block This block supports up to 8 external port lines each one configurable as input or output. A change on an input line may cause an interrupt (if not masked). The user has access to the port configuration and information via the appropriate registers of the P interface. PLL and Clock Block The PLL generates all frequencies supporting the H.1x0, SCbus, MVIP, H-MVIP busses. The internal phase-locked loop (PLL) generates all bus frequencies synchronized to a selected reference signal. The output frequency tolerance is equal to the input frequency tolerance. The PLL operates from a 16.384 MHz, or 32.768 MHz external crystal, oscillator. According to the H.1x0 specification the input frequency tolerance must be 32 ppm or less.
Preliminary Data Sheet
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PRELIMINARY Architectural Description
3.3
Switching Factory
As shown in Figure 8 the switching factory comprises the input/output data memory and the input/output data handler with the programmed connections. The I/O controller handles all lines operating at the same or different data rate. To establish a connection the user must only program the source line with time-slot and the destination line with the time-slot. The internal controller (data handler) writes the connection in a connection descriptor list and stores this list in the connection data handler. The programming procedure is described in Chapter 6. The incoming time-slot will be stored in the input data memory controlled by the input handler. The output handler controls the constant, minimum delay and subchannel switching.
3.3.1
Switching Modes
The SWITI family supports a various number of switching modes. All modes are described in the following chapters.
3.3.1.1
Minimum and Constant Delay
Each connection independent of the addressed buses can be determined to be a constant delay or minimum delay connection. Constant delay means that any input timeslot or subchannel is available on the programmed output after 2 frames. Minimum delay means that the time-slot or subchannel appears at the output as soon as possible. The minimum delay depends on the chosen connections and the possible range is between 0 and 2 frames, up to 3 frames in rare cases. An application note which describes the possible connection and minimum delays is available.
3.3.1.2
Subchannel Switching
Subchannel switching is applicable to both the local bus and the H-Bus and has a constant delay of 2 frames. Every connection can be 1-bit, 2-bit, 4-bit, or normal 8-bit connection. It is possible to combine every kind of subchannel connection, e.g. two 1-bit time-slots with one 4-bit time-slot to one output time-slot. Please refer to Chapter 6.11.2 for a detailed description about the programming.
3.3.1.3
Multipoint Switching
As described in the overview the multipoint-switching allows to switch several input timeslots to one output time-slot. All input data are logical AND or OR connected. This mode is selectable with the multipoint connection command. The setup (logical AND or OR) for the last connection determines all other previous programmed multipoint connections. Multipoint switching has always a constant delay. Subchannel switching is not supported.
Preliminary Data Sheet
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PRELIMINARY Architectural Description
3.3.1.4
Broadcast Switching
Broadcast switching allows to distribute one incoming time-slot to different output timeslots. The input and output mechanism is the same as the normal constant delay connection mode with subchannel switching. Minimum delay is also supported without subchannel switching. A table with the possible connections and minimum delays will be provided. The broadcast connection is programmed in the same way as a normal connection. The output time-slots can be released with the disconnect part of broadcast command. The last connection must be released with the normal disconnect command. Subchannel Broadcast It is possible to program one input time-slot as broadcast subchannel connections. That means the bits from the input time-slot are used in several broadcast connections related to one ore more output time-slots. The output time-slots must be released with the disconnect part of broadcast command. The last subchannel connection must be released with the normal disconnect command. (Please refer to Chapter 6.11.4 for an example)
3.3.1.5
Bidirectional Switching
The input and output mechanism is the same as the normal constant delay or minimum delay connection. The exception for the internal data handling is explained in the following figure. Since the internal state machine has to calculate the belonging connection the time to program a bidirectional connection is twice as the time to program a normal connection. There is a special command to program a bidirectional connection. A bidirectional connection can only be programmed on a available time-slot and input/ output line.
Preliminary Data Sheet
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PRELIMINARY Architectural Description
Port 0 Local Bus
TS 10
minimum delay
TS 10 Port 0
Port 1 Local Bus
TS 20
TS 20 Port 1
Issued Command SPA = 0 ITSA = A DPA = 1 OTSA = 14 CCMD = 09 Swap SPA and DPA Swap ITSA and OTSA
Internal SPA = 1 ITSA = 14 DPA = 0 OTSA = A
TS 10 Port 0
TS 20 Port 1
switi_067.emf
Figure 9
Bidirectional Mode
3.3.1.6
Stream-to-Stream Switching
The stream-to-stream switching connection supports the interoperability for the H.1x0 bus with the MVIP and SCbus, it doesn't support the local bus lines. Every dataline can be selected for the operation. The maximum number of switching channels is eight. The following example on page 29 is using two switching channels. The stream-to-stream connection can not be established parallel to the normal connections. The output of the stream-to-stream switch is multiplexed with the output of the switching factory, with the stream-to-stream having priority. Every stream-to-stream connection must be programmed with the special command in the CMD1 register. To establish the connection the bit I2 must be set to 1 and to release the connection the bit I2 must be set to 0. If the bit I3 is set to 1 all stream-to-stream connections will be released. The STR bit in the ISTA1 register indicates that one or more stream-to-stream connections are set (see also Chapter 6.2). A internal control
Preliminary Data Sheet 27 2001-11-16
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PRELIMINARY Architectural Description
logic avoids a wrong selection of the possible stream-to-stream connections and thus prevents bus collisions. The main application of the stream switch is to provide an inter-rate exchange highway allowing legacy bus devices to exchange data even though they operate at different rates with a minimum delay of zero frames. The stream-to-stream connections starts with the first frame and the switching possibilities are determined by the highest bit rate and can be seen as a repetition of same time-slot (TS) connections from one data line to another data line. If the first TS switching sequence is finished it starts with the same sequence from the next available time-slots. Table 10 shows the possible time-slot connections. Table 10 Input Data Stream Rate 2.048 Mbit/s Stream-to-Stream Connection Mapping Output Data Steam Rate 2.048 Mbit/s 4.096 Mbit/s 8.192 Mbit/s Mode Time-Slot Connection Partition 0 0 1 0 1 2 3 4.096 Mbit/s 2.048 Mbit/s 4.096 Mbit/s 8.192 Mbit/s 8.192 Mbit/s 2.048 Mbit/s 0 1 0 0 1 0 1 2 3 4.096 Mbit/s 8.192 Mbit/s 0 1 0 0 to 1, 1 to 2, 2 to 3, 3 to 4,....., 31 to 0 0 to 2, 1 to 4, 2 to 6, 3 to 8,....., 31 to 0 0 to 3, 1 to 5, 2 to 7, 3 to 9,....., 31 to 1 0 to 4, 1 to 8, 2 to 12, 3 to 16,...., 31 to 0 0 to 5, 1 to 9, 2 to 13, 3 to 17,...., 31 to 1 0 to 6, 1 to 10, 2 to 14, 3 to 18,...., 31 to 2 0 to 7, 1 to 11, 2 to 15, 3 to 19,...., 31 to 3 0 to 1, 2 to 2, 4 to 3, 6 to 4,....., 62 to 0 1 to 1, 3 to 2, 5 to 3, 7 to 4,....., 63 to 0 0 to 1, 1 to 2, 2 to 3, 3 to 4,....., 63 to 0 0 to 2, 1 to 4, 2 to 6, 3 to 8,....., 63 to 0 0 to 3, 1 to 5, 2 to 7, 3 to 9,....., 63 to 1 0 to 1, 4 to 2, 8 to 3, 12 to 4,....., 124 to 0 1 to 1, 5 to 2, 9 to 3, 13 to 4,....., 125 to 0 2 to 1, 6 to 2, 10 to 3, 14 to 4,....., 126 to 0 3 to 1, 7 to 2, 11 to 3, 15 to 4,....., 127 to 0 0 to 1, 2 to 2, 4 to 3, 6 to 4,....., 126 to 0 1 to 1, 3 to 2, 5 to 3, 7 to 4,....., 127 to 0 0 to 1, 1 to 2, 2 to 3, 3 to 4,....., 127 to 0
Preliminary Data Sheet
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PRELIMINARY Example: D0 = input stream with 2.048 Mbit/s, D3 = output stream with 8.192 Mbit/s, mode 2 D3 = input stream with 8.192 Mbit/s, D1 = output stream with 4.092 Mbit/s, mode 1 Architectural Description
Frame Boundary D3@8.192 Mbit/s D1@4.096 Mbit/s D0@2.048 Mbit/s
124 125 126 127 0 1 2 3 4 5 6 7
62
63
0
1
2
3
31
0
1
switi_059.emf
Figure 10
Example for Stream-to-Stream Switching
3.3.1.7
Message Mode
The message mode allows to send a predefined 8-bit data value in a defined time-slot on a dedicated destination port. Message mode is started or stopped via register CCMD. The data value to be send is predefined in register MV. The time-slot and the destination port is is defined in register OTSA and register DPA.
3.3.2
Parallel Mode for Local Bus
The parallel mode can be set with the 'set parallel mode' command in the configuration command register. This command set the first 8 input lines and the first 8 output lines of the local bus as parallel bus. The data rate for all lines must be 2.048 Mbit/s. If the parallel mode is enabled all included lines will be set to 2.048 Mbit/s automatically. If the parallel mode is disabled all lines will keep the data rate of 2.048 Mbit/s until a new data rate will be programmed for the selected line. The internal S/P-converter is bypassed. The 8 bit data stream per time-slot is distributed on 8 data lines, one bit for every line. The least significant bit is assigned to line 0 and the most significant bit is assigned to line 7. To program a connection line 0 must be used for this special parallel data port. The bit shift value must only be programmed for port 0 and this value will be assigned to the other 7 ports automatically. The initialize sequence is described in Chapter 6. The switching data handling is the same as the data handling for constant delay or minimum delay mode. A timing diagram is provided in the timing diagram chapter (see "PCM Parallel Mode Timing" on page 131).
Preliminary Data Sheet
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PRELIMINARY Architectural Description
3.3.3
Switching Block Error Handling
The normal procedure to establish a connection is explained in Chapter 6. The way to program a new connection for a specific time-slot and data line is to release the connection and to program the new connection. The SWITI switching concept provides an internal error handling to detect errors in the switching chain caused by a programming error. A programming error can occur because of noises on the data lines, software errors, etc. A programming error is defined as follows: - if a non existing connection (minimum, constant delay, or message) will be released. - or if a existing minimum delay connection will be established. If a programming error or a connection memory overflow is detected the interrupt bit CON in the IESTA2 register will be set. In this case the last connection which was tried to establish or to release is not valid. The switching mechanism is not affected and will continue with the switching process. For debug purposes the SWITI has the capability to write out the content of the complete connection memory and data memory via the microprocessor interface. This procedure is described in Chapter 3.3.4. It is recommended to track all established and connections with the specific customer application software. For debug purpose it is useful to compare the contents of the switching memory with the virtual connections in the application software.
3.3.4
Analyze Connection and Data Memory
With the special command "memory dump enable" in the connection command register (CCMD) it is possible to read the complete memory in a defined sequence from the CON register with a 8-bit P access. This feature can be used only for analyze purposes. The command disables the complete switching function as far as all data lines (PCM/ H.1x0) are set to high impedance. If the command is set and after the specific recovery time (200 ns) the connection chain and data memory can be read sequentially by a P access to the CON register. The internal controller writes the next 8-bit memory data in the CON register if the P read access is finished. That means there is a specific recovery time for the P to the next CON read access. The internal memory dump controller reads the present memory contents of the input chain memory, data memory and output chain memory. During the memory dump the internal state machine will loose the synchronization with the external frame structure. Therefore a software reset must be issued and the device must be programmed again, except the clock configuration.
Preliminary Data Sheet
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PRELIMINARY Architectural Description
Infineon Technologies provides a software driver to recalculate the chain and to recover the current connections. For a detailed explanation of the internal structure and the software driver please refer to the application note "Connection Memory Dump".
3.4 3.4.1
Clock Generator and PLL General Overview
The following figure gives an overview about the clock generator with the integrated PLL.
CT_FRAM E_B CT_FRAM E_A /FR_COM P
EC LKI EC LKO H -M O D E PFS PD C SC LK C 2,/C 4,C 16 C T_C 8_A/B C T_N ETR EF_1 C T_N ETR EF_2 N TW K_1 N TW K_2 /FR _C OM P
O SC
R eset = : 1
D IV :1 :2
D IV :8
HTSI
8 kH z C T_C 8_A /C T_FR AM E_A C T_C 8_B /C T_FR AM E_B
8.192M H z 3 2 R eset D IV :1 :2 :4 :8 : 64 : 192 : 193 C ntr. Logic 8 kH z D PLL #1 norm . Operation = 49.152 M H z APLL Bypass = 16.384/32.768 M H z 2.048M H z 4.096M H z 16.384M H z
H -M VIP C 2,/C 4,/C 16 /FR _C OM P M VIP-90 C 2,/C 4 /FR _C OM P
APLL D IV :1 :2 :4 :8 : 64 : 192 : 193 3 2
phase alignm ent
fram e alignm ent
M ain D IV
Bypass D PLL #2 2.048M H z R ef. clock m ux Slave path
Program m able
H .1x0 autom atic SC bus SC LK, SC LKx2 Fsync 8 kH z 8.192M H z 2.048M H z 4.096M H z 16.384M H z
/C T_FR AM E_A /C T_FR AM E_B SC LK SC LKx2 C 2,/C 4,C 16 C T_C 8_A/B
PC M D IV
M UX M aster/Slave
PD C 2,4,8,16 M H z PFS
16.384M H z from M ain D IV GPC LK[7:0] int. Frequency Input APLL
NTW K_1 NTW K_2 CT_NETREF_1
NTW K_1 NTW K_2 CT_NETREF_2
SC LK C2 /C 4 /C 16
D IV :1 :2 :4 :8
C T_C 8_A
D IV :4 D IV :4
D IV :8 : 32 : 2048
FR AM E SM
GPC LK[7:0]
C T_C 8_B
not used in M-Mode
C T_N ETR EF_1
C T_N ETR EF_2
PD C
PFS
sw iti_058.em f
Figure 11
SWITI Clock Generator
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PRELIMINARY Architectural Description
The SWITI clock generator provides all necessary clock signals for the SWITI PCM (local bus) and H.1x0 interfaces. Since the device is a H.1x0 master capable device there are two digital PLLs which can be locked to different network reference signals. The digital PLL synchronizes the external crystal or oscillator to the selected reference clock. The digital PLL (DPLL) will be bypassed if the selected reference signal is >= 2.048 MHz. The input signal for the analog PLL (APLL) is 2.048 MHz in normal operation mode. The APLL is used for multiplying the 2.048 MHz clock into a 49.152 MHz clock and to generate all clock signals for the PCM and H.1x0, and general purpose clock signals. The SWITI has an on-chip oscillator which allows the user to connect an external 16.384 MHz or 32.768 MHz crystal. Instead of using the crystal it is possible to assign a 16.384 MHz, or 32.768 MHz oscillator to the ECLKI pin. After the power-on or hardware reset the APLL is bypassed. The APLL will be synchronized (after approximately 750 s) to the external crystal or external oscillator if the command 'set external frequency' is set. This command must be used otherwise the internal working frequency is equal to the external input frequency and the SWITI will not work properly. If the APLL is locked the status bit 'APLL' in the ISTA1 register will be set. Note: After the reset it is necessary to program the correct crystal or oscillator value as first programming step. Otherwise the operation frequency for the SWITI is not correct.
3.4.2
Features
Analog PLL (APLL)
Low cycle-to-cycle jitter < 1 ns Natural frequency fg = 15 kHz Damping factor = 0.7 Input Frequency = 2.048 MHz in any case Output Frequency = 49.152 MHz, duty-cycle = 50 % Rule behavior = change of output frequency in range of 0 - 10% in response to changes of input frequency * phase slope of output frequency equal to phase slope of input frequency Note: It is necessary to provide a "noise free" analog power (VDDA/VSSA) to reduce the internal jitter of the APLL. These pins must be decoupled from the digital power (VDD/VSS), see also the available Application Note "Layout Notes".
* * * * * *
Preliminary Data Sheet
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PRELIMINARY Architectural Description
3.4.2.1
Functional Description
iref fref
frequency detector
up/down
UP/DOWN Counter
cw
DAC
igrob
current reference
ibias ibias
fin
fref
phase/ frequency detector
incr decr
Charge pump
VTOI
iint
CCO
fosc
iprop
n-divider
locked pu
Timer
Figure 12
Block Diagram of APLL
The value of the output frequency depends of the programming of the n-divider. The chosen output frequency for the SWITI is 49.152 MHz and the input frequency is 2.048 MHz. The macro consists of a digital and an analog PLL which are working together. During start-up only the digital one is enabled and makes a coarse adjustment, so that the technology dependency of the circuit is compensated. Afterwards the digital PLL is disabled again and the analog one is switched on for normal operation. The digital PLL is of first order and consists of a frequency detector (FD), an up/down counter, a digital-to-analog converter (DAC) and a current controlled oscillator (CCO). The FD detects any frequency difference between the reference clock (fref: input clock fin = 2.048 MHz) and the divided oscillator clock. The output signal controls the counter. If the reference frequency is higher than the divided oscillator frequency the counter is increased. The counter output drives a current steering DAC which controls the input current of the internal oscillator. Its current rises and the output frequency increases until both frequencies are equal. The digital PLL is enabled after reset or power up and is disabled after 750 s (lock time of PLL). The counter keeps its value and the DAC output current irough is constant until the digital PLL is reseted.
Preliminary Data Sheet
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PRELIMINARY Architectural Description
The second order analog PLL consists of a phase/frequency detector (PFD), a charge pump (CP), a loop filter and the CCO. The PFD which is sensitive to the rising edge detects any phase or frequency difference between the input clock (fref) and the divided output clock (feedback) and generates a control signal proportional to the phase difference. The output signals up and down cause the charge pump to modulate the amount of charge in the low pass filter (VTOI) for the integral part (iint) and to feed current into the CCO for the proportional part (iprop). With these two currents and the DAC output irough the CCO is controlled. If feedback is leading fref, the oscillator is too fast. The down signal is activated and the CP subtracts some current iprop. When fref is in phase with the feedback the PLL will hold the control current at that level and phase lock will be achieved. Thus through this negative feedback arrangement, the PLL causes the feedback and fref signals to be equal with minimum phase offset. If the analog PLL becomes unstable, a signal pllko is generated which resets the digital PLL.
20lg |H(f)| +8 +6 +4 +2 0 -2 -4 -6 -8 -10 -12 -14 -16 -18 -20
0,1
0,2 0,3 0,4
1
2
3
4
10
f/fg
Figure 13
APLL - Jitter Transfer Function
3.4.2.2
Jitter-Transfer-Function
Jitter transfers or jitter attenuation refers to the magnitude of jitter at the output of a device for a given amount of jitter at the input of the device. Input jitter is applied at various amplitudes and frequencies, and output jitter is measured with various filters depending on the applicable standards.
Preliminary Data Sheet
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PRELIMINARY Architectural Description
Figure 13 shows the jitter transfer function of the SWITI device. The cutoff frequency of the integrated low pass filter is fg = 15 kHz.
3.4.3
Master-Slave Selection
For a proper working PLL and clock fallback mechanism it is necessary to select the part as master or slave with the "select master/slave" command in the CMD1 register. If the M-Mode is used it is not allowed ot use the special master command. As described in Chapter 3.4.6 this command must be used to finish the clock generator configuration and/or to finish the H.1x0 fallback configuration. The PLL reference source can be selected with the "PLL Primary Reference for Master Selection" command, or with the "PLL Source Selection" command.
3.4.4
Phase Alignment
If the phase alignment function is enabled all PLL output signals and the main divider are edge synchronized with the PLL clock input. If the selected reference signal is less than 2.048 MHz the edge synchronization resolution depends on the selected external crystal/oscillator frequency. If the phase alignment function is disabled the PLL output frequency (49.152 MHz) is edge synchronized with the PLL input frequency and the main divider output frequencies are edge synchronized with PLL output frequency. An example of phase alignment functionality is shown in Figure 14. Phase alignment is required to keep the output signals in phase relative to the input signals (e.g. C8A relative to C8B). After reset phase alignment is automatically activated in secondary master and slave mode and turned off in master mode. Note: The phase alignment should be disabled for all reference frequencies < 2.048 MHz.
P h a s e alig n m en t disabled
A P L L in pu t (2.04 8 M H z) A P LL o utp u t (4 9 .15 2 M H z)
M a in divid er ou tp ut p h ase diffe re nce
P h a s e alig n m en t enabled
A P L L in pu t (2.04 8 M H z) A P LL o utp u t (4 9 .15 2 M H z)
M a in divid er ou tp ut
sw iti_0 91 .em f
Figure 14
Example of Phase Alignment
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PRELIMINARY Architectural Description
3.4.5
PLL Synchronization
As shown in Figure 11 there are several possibilities to synchronize the PLLs. For the synchronization it is necessary to distinguish between the different operational modes (H.1x0 with PCM, only PCM). The PLL needs approximately 750 s to lock to the selected reference frequency. For the frame synchronization the clocking unit needs additionally two frames to synchronize the incoming frame with the generated frame. This frame synchronization will be enabled if the device is configured as H.1x0 slave, H.1x0 secondary master, and compatibility bus slave.
3.4.5.1
PLL Synchronization H-Mode
The following operational modes apply to the HTSI H-Mode. - H.1x0 Master and PCM Master In this mode the reference frequency must be selected by software according the H.1x0 specification. The H.1x0 and PCM clock synchronization is guaranteed by the fact, that the synchronized 2.048 MHz clock, generated from one of the digital PLLs, is used as input clock for the analog PLL, used for the generation of all necessary clocks. If the reference frequency is equal or higher than 2.048 MHz the digital PLL is bypassed and the reference signal is connected with analog PLL. The beginning of the PCM frame is equal with the beginning of the H.1x0 frame. - H.1x0 Slave and PCM Master For the H.1x0 Slave mode both digital PLLs are bypassed and the input signal for the analog PLL comes from one of the selected slave path clock sources. The PCM clock signals are synchronized to the H.1x0 selected input reference clock signal and there isn't a phase difference between the signals. The beginning of the PCM frame is equal with the beginning of the H.1x0 frame. This is guaranteed by the fact, that the related frame signal to the selected clock signal is used for the frame synchronization. - H.1x0 Master and PCM Slave This mode is not allowed, since the PCM frame start is not synchronized with the H.1x0 frame start. - H.1x0 Slave and PCM Slave The PDC and PFS signals must be equal to the highest selected PCM datarate and must be sourced. The incoming PCM clock/frame signals must be derived from the same clocking source as the H.1x0 clocks or from a master with the same reference clock as the H.1x0 master. Since there isn't a elasticity switching buffer in the SWITI the incoming clock must be synchronized, must have the same phase and the H.1x0 frame start must be equal to the PCM frame start.
Preliminary Data Sheet
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PRELIMINARY Architectural Description
3.4.5.2
PLL Synchronization M-Mode
The PLL reference source can be selected from the primary reference master source (PFS, PDC, NTWK_1/_2). If the selected reference signal is less than 2.048 MHz the main digital PLL is used to synchronize the analog PLL. The digital PLL is sourced from the external oscillator, or crystal. In this case the analog PLL output frequency tolerance is equal to the external oscillator/crystal frequency tolerance. Furthermore the analog PLL can be sourced directly from the external oscillator, or crystal, or from the PDC input. All generated output frequencies will have the same tolerance as the selected input frequency.
3.4.6
PLL Error Handling
The SWITI in H-mode has an integrated control logic to detect possible PLL configuration errors. If one of the errors (see below) occurred the clock fallback mechanism and the PLL functionality is not guaranteed. The control mechanism starts with the command 'Set as H.1x0 Master/Slave (HTSI H-Mode)' in the CMD1 register. That means that the mentioned command finished the clock generator configuration. As shown in Figure 11 there is a cntr. logic for the two APLL multiplexer implemented. The first multiplexer is used to select one reference source for the master mode and the second multiplexer is used to decide between the slave or master path. The main task for this control logic is to make sure that the input signal for the APLL derives from the internal oscillator (external oscillator) after the reset. The second task is to control the input signal for the APLL during the normal operation and to decide whether the programmed combination is correct. If one of the following combinations occur, the control logic selects the internal oscillator, resets the complete clock generator configuration and an interrupt will be generated (-> wrong PLL source programming). Configuration errors which will be detected: HTSI H-Mode Master configuration - PLL2 source was selected (slave path) HTSI H-Mode Slave configuration - PLL main or secondary master reference was selected Furthermore the fallback state machine controls the logic to multiplex the necessary signal for the fallback mechanism. Since there are redundant paths for the reference clock and also for the slave clocks the clock fallback time depends only on the multiplexer delay time.
3.4.7
Clock Fallback
This chapter must be read if the SWITI is used as H.1x0 device (H-mode).
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PRELIMINARY Architectural Description
3.4.7.1
Clock Signal Monitoring
To support the clock fallback mechanism the SWITI has the capability to monitor the CT_CA (CT_C8_A, CT_FRAME_A), CT_CB (CT_C8_B, CT_FRAME_B) clocks additional with the selected primary PLL reference, and to monitor the interoperability clock signals. The SWITI reports every clock failure to the host with a interrupt if it is not masked. If the interrupt is masked the status of the clock errors can be read from the IESTA1 and IESTA2 registers (polling). The H.1x0 clock signal monitoring will start immediately after programming a new reference clock. The process is finished with the command 'master slave' from the CMD1 register. The following monitoring requirements for H.1x0 must be meet: - A received rising edge of CT_C8_A/B (both signals must controlled independently) doesn't arrive within 35ns of the expected edge. or - There are not exactly 1024 clock periods per frame. If one of these requirements are not meet an interrupt will be generated (if not masked) to inform the system software that one of the clock circuits (A or B) is failed. The following monitoring requirements for the interoperability clock signals must be meet. The FR_COMP is monitored in conjunction with the selected primary PLL reference (master) signal or with the selected PLL source (slave). MVIP - A received rising edge of C2, C4, or C8, or C16 doesn't arrive within 40 ns of the expected edge. or - There are not exactly 256, or 512, or 1024, or 2048 clock periods per frame SCbus - A received rising edge of SCLK doesn't arrive within 40 ns of the expected edge. or - There are not exactly 256 (SCLK=2.048 MHz), 512, or 1024 clock periods per frame. NTWK Signals A received rising edge of the NTWK signal doesn't arrive within 80 ns of the expected edge.
Preliminary Data Sheet
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PRELIMINARY Architectural Description
3.4.7.2
Clock Fallback Mechanism
The clock fallback mechanism can be switched on with the special command "H.1x0 Fallback Mechanism and Clock Monitoring" and the related instruction bits. As described in the H.1x0 specification there are two different fallback path's in the fallback state machine. The instruction "fallback from main to secondary reference (primary master)" in conjunction with the command "automatic switch back to main ref." covers the "primary NTWK link fails" path. The correct reference (main and secondary) as described in the H.1x0 specification must be programmed, e.g. NTWK or CT_NETREF. The instruction "fallback from main to secondary reference (secondary master)" and "from A clock to B clock (Slave)" covers the "primary master clock circuit fails" path in the fallback state machine.
CT_C 8_A; CT_FR AM E_A CT_C 8_B; CT_FR AM E_B CT_N ETREF_1 CT_N ETREF_2
N T W K _ 1 fa ils P rim a ry M a ste r N T W K _ 1 re tu rn s P rim a ry M a ste r
N TW K_1
NTW K_2
NTW K_1
N TW K_2
T h e d o t m e a n s th e A clo ck d rivin g P L L is syn ch ro n ize d to th is re fe re n ce clo ck
sw iti_ 0 2 4 .w m f
Figure 15
Clock Fallback of Primary Master
The primary master is synchronized to a reference clock (NTWK or CT_NETREF) and drives the CT_C8_A and CT_FRAME_A clocks. Figure 15 shows a configuration example. If the primary network reference clock (NTWK_1) fails the device automatically synchronizes to the secondary network reference clock (NTWK_2). If the primary reference clock returns the device may synchronize to it again automatically or by software command (depends on configuration). If not masked the failure is reported by an interrupt.
Preliminary Data Sheet 39 2001-11-16
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PRELIMINARY Architectural Description
C T_C8_A; CT_FR AM E_A C T_C8_B; CT_FR AM E_B CT_N ETR EF_1 CT_N ETR EF_2
C T _ C 8 _ A fa ils S e co n d a ry M a ste r S e co n d a ry M a ste r
N TW K_1
NTW K_2
N TW K_1
N TW K_2
T h e d o t m e a n s th e B clo ck d rivin g P L L is syn ch ro n ize d to th is re fe re n ce clo ck
sw iti_ 0 2 5 .w m f
Figure 16
Clock Fallback of Secondary Master
The secondary master is synchronized to CT_C8_A, CT_FRAME_A and drives CT_C8_B and CT_FRAME_B. If one of the CT_A clocks fail the device may synchronize automatically or by software command (depends on configuration) to another reference clock (NTWK or CT_NETREF). Figure 16 shows a configuration example. If not masked the failure is reported by interrupt. The reference and the fallback must be programmed again if the automatic fallback to the new reference was performed. Any fallback and re-programming will be performed without data loss in the device.
Preliminary Data Sheet
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PRELIMINARY Architectural Description
C T_C8_A; CT_FRAM E_A C T_C8_B; CT_FRAM E_B CT_N ETR EF_1 CT_N ETR EF_2
C T _ C 8 _ A fa ils S la ve S la ve
N TW K_1
N TW K_2
NTW K_1
N TW K_2
T h e d o t m e a n s th e in te rn a l clo ck P L L is syn ch ro n ize d to th is re fe re n ce clo ck T h e sq u a re m e a n s th e N e tre f p ro vid in g P L L is syn ch ro n ize d to th is re fe re n ce clo ck
sw iti_ 0 2 6 .w m f
Figure 17
Clock Fallback of Slave
The slave is synchronized to CT_C8_A and CT_FRAME_B. If the clock fails the slave synchronizes automatically or by software command to CT_C8_B and CT_FRAME_B. If not masked the failure is reported by interrupt. In the case of an automatic fallback to the CT_CB or CT_CA clocks the new reference must be programmed. The fallback and the re-programming of the source will be done without any data loss regarding the Stratum 4e specification. Additionally the fallback must be issued again if needed.
Preliminary Data Sheet
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PRELIMINARY Architectural Description
3.5
Loops
The loop command in the configuration command register CMD2 provides support for automatic PCM-PCM and H.1x0-H.1x0 loops. - PCM-PCM loop All input lines are pad connected with the corresponding output line. H.1x0-H.1x0 loop The first 16 H-bus lines are pad connected with the corresponding upper 16 H-bus lines. e.g. H0 -> H16; H1 -> H17; ....... After the loop disable command was set the lines will be set in high-impedance after approximately two frames.
3.6
Read SWITI Configuration with Indirect Register Addressing
Since the SWITI configuration can be programmed with defined instructions in the CMD1 and CMD2 registers it is possible to read the current configuration through the indirect access registers. The indirect addressing is started by writing one of the five read configuration commands in the CMD2 register. The five commands can be separated in two groups, internal configuration and external line configuration. The internal configuration, e.g. clock generator, IREQ pin can be read with command "Read Configuration". The internal settings are decoded with the instruction bits I3..0. The data rate for the PCM and H.1x0 interface can be read with the "Read PCM / H.1x0 Line Configuration" commands and to get the GPCLK line configuration and the bit shift value the "Read GPCLK Configuration" and "Read Bit/Clock Shift Configuration" must be issued. The TSV and CON registers contain the required information after the internal read process is complete. The recovery time is 240 ns. To read the correct configuration data from the TSV register it is not allowed to use the command "Read Time-Slot Value" before the TSV register has been read.
Preliminary Data Sheet
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PRELIMINARY Architectural Description
3.7 3.7.1
Power-On and Reset Behavior Hardware Reset
There are three independent low active reset pins: RESET, CT_RESET and TRST. If the RESET or CT_RESET (in conjunction with the mode pins M-Mode and H.110 Mode) pin is activated, it immediately places all outputs and I/O ports into tri-state, except the ECLKO pin. After the reset process the correct external frequency must be set with the command 'Set external frequency' accordingly. This command starts the configuration process for the APLL. The APLL is locked after 750 s. During this period the APLL is bypassed and the internal frequency is 2.048 MHz. If the APLL is locked the internal frequency will be 49.152 MHz. Individual output sections must be enabled by setting the command in the configuration command register CMD1, or CMD2. Internally all state machines, counters and registers are cleared and set to their defined reset value. The H.110 controller is in the reset state and all H.110 I/O pins are tri-stated as long as the CT_RESET pin is asserted. (see "CT_RESET" on page 48) The RESET and CT_RESET pins don't control the boundary scan register and TAPcontroller. If the TRST pin is asserted the TAP-controller will go into the Test-Logic-Reset state and all boundary scan elements are bypassed. All outputs and I/O-pins are controlled by the core logic and are tristated according to the programmed functionality or the core reset condition (pin RESET). The hardware reset must be issued for a minimum of 1 s, for more details please refer to the chapter "Hardware Reset Timing" on Page 146.
3.7.2
Software Reset
The software reset is accomplished by setting the 'Set Software Reset' command in the CMD2 register. The software reset clears the complete device except the clocking unit and the temporary microprocessor registers (e.g. CMD1). The software reset can be deactivated with the 'Set Software Reset' command. During software reset the microprocessor interface doesn't accept any other commands for a minimum of 1 s.
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4
4.1
Description of Interfaces
Local Bus Interface (PCM)
The local bus is a PCM interface consisting of input and output data lines (IN, OUT), a PCM data clock PDC and a frame synchronization signal PFS.
C lock S lave PFS PDC IN OUT P C M I/O PFS PDC IN OUT
C lock M aster
P C M I/O
sw iti_037.w m f
Figure 18
PCM Interface Configurations
The PFS Frame Sync is a 8 kHz signal and delimiting the frame. This input signal is used by the SWITI to determine the start of a frame. A frame is divided into 8-bit wide time-slots. The amount of time-slots within a frame depends on the selected data rate of PDC which can be 2.048 Mbit/s, 4.096 Mbit/s, 8.192 Mbit/s, 16.384 Mbit/s. The PFS input has a Schmitt-Trigger characteristic. The PDC Data Clock input supply the SWITI with a data clock. It can be operated with 2.048 MHz, 4.096 MHz, 8.192 MHz, or 16.384 MHz data rate clock depending on the selected highest data mode. The PDC clock signal must be equal or higher as the highest data rate. The PDC input has a Schmitt-Trigger characteristic. A clock slave must receive PFS and PDC whereas a clock master drives these signals. To enable or disable the signals for the clock master the command 'PCM Clock Input/ Output Selection' must be issued. The time-slots are transmitted and received via 16 input and 16 output lines (IN[15:0], OUT[15:0]). The input lines have a Schmitt-Trigger characteristic. The output lines have tristate outputs with push-pull characteristic. For every time-slot not participating to a connection the output is high impedance. With the special command "Local Bus (PCM) Standby" in the CMD2 register it is possible to set all PCM lines in a high impedance state during the normal operation mode. All PCM lines are in high impedance state after the reset process and must be enabled with the "Local Bus (PCM) Standby" command. All lines which are not participating on a switching operation are in high impedance state and the time-slot information on the input lines are discarded automatically.
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PFS
0 7 0 1 7
D a ta R a te o f th e S e le cte d L in e In p u t 0 O ffse t o f TS0 In p u t 1 O ffs e t o f TS0
O u tp u ts O ffs e t o f TS0
sw iti_ 0 3 9 .e m f
Figure 19
PCM Bit Shifting
For each PCM input line the offset of time-slot zero can be adjusted in a range from 0 to 7 bit in half clock resolution before or after the PFS rising edge. For all output lines the offset of time-slot zero can be adjusted in a range from 0 to 7 bit in half clock resolution after the PFS rising edge. The resolution depends on the selected data rate that means the resolution doesn't depend on the PDC signal. After the reset process the bit shift is disabled for all lines. That means the time-slot 0 starts with the rising edge of PFS. All input data will be sampled with falling edge of the selected data rate and the output data are valid with the rising edge of the selected data rate.
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4.2
H-Bus Interface
VDD
V SS
IN [1 5 :0 ] O U T [1 5 :0 ] PFS PDC
C T _ D [3 1 :0 ] /C T _ F R A M E _ A C T_C 8_A /C T _ F R A M E _ B C T_C 8_B
G e n e ra l P u rp o s e C lo c k s
C T _ N E T R E F (_ 1 ) CT_N E TRE F_2
G P IO
HTSI P EB 2xxxx
/C T _ E N /C T _ R E S E T /F R _ C O M P S C LK
M is c .
TRST TC K TM S TDI TDO
S C L K x 2 * / S C L K -D C2 /C 4 /C 1 6 + /C 1 6 -
D [7 :0 ]
A [4 :0 ]
RD DS
WR R /W
CS
IR E Q IR E Q
RESET
A LE
MODE
switi_002.wmf
Figure 20
H-Bus Interface in H.100 Mode
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C T _F R A M E _ A : 8 kH z; d rive n b y m aste r A C T _C 8_ A : 8 .19 2 M H z; d riven b y m a ste r A ; 50 % d uty cycle C T _F R A M E _ B : 8 kH z; re du nd an t; d rive n by m aste r B C T _C 8_ B : 8 .19 2 M H z; re du nd an t; d rive n b y m aste r B ; 5 0% du ty cycle C o re S ign als 32 C T _D [3 1:0 ]: 40 96 T S C T _N E T R E F _ 1: 8 kH z, 1.54 4 M H z, 2.04 8 M H z; an y du ty cycle C T _N E T R E F _ 2: 8 kH z, 1.54 4 M H z, 2.04 8 M H z; an y du ty cycle C T _E N : ind ica tio n tha t J4 is fully se ated C T _R E S E T F R _C O M P : 8 kH z; S C b us (F syn c*) In te r-op era bility w ith A N S I V IT A 6 S C bu s S C L K : 8 .19 2 M H z; S C b us S C L K -D : 8.1 92 M H z; S C bu s
sw iti_ 0 3 3.e m f
Figure 21
H-Bus Interface in H.110 Mode
Note: The frequency of SCLK in H.110 mode is 8.192 MHz only.
4.2.1
CT_C8(A/B) and CT_FRAME(A/B)
The functional timing relationship of the CT Bus clocks can CT_FRAME can be found in the chapter "H-Bus and PCM (Local Bus) Frame Structure" on page 132. The CT_FRAME is a 8 kHz signal and delimiting the frame. The negative pulse, nominally 122 ns wide marks the beginning of the first bit of the first time-slot. The CT_C8 is the 8.192 MHz bit clock. The duty cycle of this signal is nominally 50%. A H.1x0 slave must receive CT_C8 and CT_FRAME whereas a clock master drives these signals.
4.2.2
Dataports
There are 32 bidirectional pins available for accessing the H-bus. The frame structure is shown in Chapter 7.3. For every pin there is a tri-state controller. The CT_EN signal enables the tri-state controller for the H.110 data lines. With the special command "PCM
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and H.1x0 Standby" in the CMD2 register it is possible to set all H.1x0 lines in a high impedance state during the normal operation mode. All H.1x0 lines are in high impedance state after the reset process and must be enabled with the "PCM and H.1x0 Standby" command. All lines which are not participating on a switching operation are in high impedance state. The default data rate is 8.192 Mbit/s in accordance to the H.100/H.110 specification. With the configuration command register it is possible to select a individual data rate from 2.048 Mbit/s, 4.096 Mbit/s, and 8.192 Mbit/s in accordance to support the interoperabilitiy busses.
4.2.3
CT_EN
The CT_EN signal must be implemented in an identical manner to the implementation of the BD_SEL# signal as specified in the PICMG 2.1 CompactPCI Hot Swap specification by connecting CT_EN to a logic high (de-asserted) through a 1.2K 5% resistor or current source equivalent. The CT_EN signal indicates that a PCI board is fully seated. The H.110 interface logic is enabled if the CT_EN signal is active (logic low level enables all H.110 ports, PCM ports, and clock signals).
4.2.4
CT_RESET
The CT_RESET must be functionality and electrically equivalent to the CompactPCI signal RST#. The device must respond to the CT_RESET signal when it is asserted. All H.110 outputs and I/Os are high impedance until the CT_RESET is released as well as the related PCM outputs and I/Os. No clocking signal can influence the internal logic during the reset state. All internal state machines and counters are in a defined reset state after the CT_RESET signal is released and the connection memory is in the reset state. After the CT_RESET signal is released the device has to be configured with the configuration command register 1 and 2 (CMD1, CMD2). The RESET and CT_RESET (in conjunction with the mode pins M-Mode and H.110 Mode) signals are logical or connected.
4.2.5
H-MVIP C16 Signals
The differential signal is driven by the clock master and used to read and write bits on the serial data lines. Time-slot boundaries align with the falling edge of C16+. The C16 signal is differential. The SWITI doesn't have a integrated differential receiver/ transceiver with the required thresholds of the EIA standard RS-485. Nevertheless the differential C16+, C16- input signals are logical decoded to one internal /C16 signal if the SWITI is configured as clock slave. The C16- is the inverted C16+ signal if the SWITI shall generate the C16+, C16- signals.
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4.3
Data Rate
The SWITI provides the programming of data rates on a per line basis for the local bus as well as for the H.100/H.110 bus. To support the H.100/H.110 bus and the interoperability bus systems all 32 H.100/H.110 data lines can operate with 2.048 MHz, 4.096 MHz, and 8.192 MHz independently. The following table shows the possible data rates for the different lines. Table 11
HTSI-M HTSI-H
Data Rates for Local and H-Bus
PCM0..7 (IN/OUT) 2/4/8/16 Mbit/s 2/4/8/16 Mbit/s PCM8..15 (IN/OUT) 2/4/8 Mbit/s 2/4/8 Mbit/s PCM16..31 (IN/OUT) 2/4/8/16 Mbit/s x H0..31 x 2/4/8 Mbit/s
All local bus lines can operate with 2.048 MHz, 4.096 MHz, and 8.192 MHz independently and up to 24 local bus lines for the HTSI in M-mode or 8 local bus lines for the HTSI in H-mode can operate with 16.384 MHz as well. Having 16.384 Mbit/s in any of the PCM0..7 lines, the corresponding (PCM0..7 + 8) lines will be deactivated (tristate). Using all PCM0...7 lines with 16.384 Mbit/s all the PCM8...15 will be then deactivated. The input and output lines are independent of each other, i.e. for a given bus line the input and the output lines can be programmed with different data rates. For the HTSI the maximum aggregate data rate supported at the input and output bus lines is 393.216 Mbit/s, (e.g. 24 lines x 16.384 Mbit/s per line = 393.216 Mbit/s, as input and/or output). The following tables show some possible configurations for the local and H-bus lines, with the highest data rate allowed. Table 12 Maximum possible data rates for HTSI in M-mode
PCM8..15 (IN/OUT) x x 8 x 8.192 Mbit/s 8 x 8.192 Mbit/s PCM16..31 (IN/OUT) 16 x 16.384 Mbit/s 16 x 8.192 Mbit/s 16 x 16.384 Mbit/s 16 x 8.192 Mbit/s H0..31 x x x x PCM0..7 (IN/OUT) 8 x 16.384 Mbit/s 8 x 16.384 Mbit/s 8 x 8.192 Mbit/s 8 x 8.192 Mbit/s
Table 13
Maximum possible data rates for HTSI in H-mode
PCM8..15 (IN/OUT) x 8 x 8.192 Mbit/s PCM16..31 (IN/OUT) x x H0..31 32 x 8.192 Mbit/s 32 x 8.192 Mbit/s
PCM0..7 (IN/OUT) 8 x 16.384 Mbit/s 8 x 8.192 Mbit/s
Note: Table 12 and Table 13 show all possibile combinations with only 8.192 Mbit/s and/or 16.384 Mbit/s for all available bus lines
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4.4
Microprocessor Interface
A standard 8-bit multiplexed or non-multiplexed P interface is provided, compatible to Intel/Siemens (e.g. 80386EX, C166) and Motorola (e.g. 68040, 68340, 68360, 801) bus systems. If the GPIO port is not needed it can be used to provide a 16-bit P interface. The 16-bit mode is determined according to MODE16 input pin. MODE16 = '0' -> 8-bit interface MODE16 = '1' -> 16-bit interface This chapter describes how to configure the P interface to each mode.
4.4.1
Intel/Siemens or Motorola Mode
The Intel/Siemens or Motorola mode for the P interface can be configured during the hardware reset process in conjunction with the ALE pin. - ALE permanently driven to 'low' => Motorola mode - ALE permanently driven to 'high' => Intel/Siemens mode - Edge on ALE => Intel/Siemens multiplexed mode A falling or rising edge on ALE during the normal operation selects the multiplexed mode immediately. With the hardware reset and the tied ALE pin it is possible to return to the Motorola or Intel/Siemens mode.
4.4.2
De-multiplexed or Multiplexed Mode
In both modes, the A-bus and the D-bus are used in parallel. The A-bus should be connected to the LSBs of AD-bus, coming from the P, also in multiplexed mode.
The next figure describes the connection to the address and data buses in the different modes.
Note: Motorola mode is used only with de-multiplexed AD bus. Intel/Siemens mode may be used with both, multiplexed or de-multiplexed AD bus.
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Multiplexed Mode P
8/16 AD 5 D A ALE ALE
SWITI
LATCH
De-multiplexed Mode P
D A 8/16 5
D A
SWITI
LATCH
`1'
ALE
Figure 22
Multiplexed and in De-multiplexed Bus Mode
Note: In both modes only the 5 LSBs of A-bus or AD/bus are connected to the Address inputs.
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4.5
General Purpose Port (GPIO)
This port consists of 8 lines each one configurable as input or output. A change on an input line may cause an interrupt (if not masked). The user has access to the port configuration and information via the appropriate registers of the P interface. Figure 23 shows an example.
Signal GPIO Pin No.
1 7
0 6
1 5
0 4
1 3
1 2
1->0 1
1 0
GPIO Direction Register
1
1
1
1
0
0
0
0
Line 7 to 4 as outputs Line 3 to 0 as inputs Changes in line 1 or line 0 cause interrupts Drive 1010 on lines [7:4] Contains current value of input lines Change on input line 1 detected
switi_055.emf
GPIO Mask Register
X
X
X
X
1
1
0
0
GPIO Output Register
1
0
1
0
X
X
X
X
GPIO Input Register
X
X
X
X
1
1
0
1
GPIO Interrupt Register
X
X
X
X
0
0
1
0
X = don't care
Figure 23
GPIO Port Configuration Example
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4.6
General Purpose Clocks
The SWITI provides 8 general purpose clock lines. With two independent commands in the CMD2 register the lines can be configured as frame group signals or individual clock signals. The last written command for a line is valid and controls the multiplexer.
4.6.1
Frame Group Outputs
Via 8 output lines it is possible to provide 8 different framing signals which are used for synchronization purpose. All signals have a period of 125 s. Their offset can be programmed individually within the PFS determined frame in a resolution of 61 ns (1/ 16.384 MHz). The default start point for the offset is the beginning of a frame (rising edge of PFS and the clock signal). The start point for the offset can be shifted for a half clock cycle, that means the second start point is determined with the rising edge of PFS and the next falling edge of the clock signal (as shown in Figure 24). The high time of the signal can also be programmed in steps of 61 ns. All frame signals can be controlled as high or low active.
12 5s
PFS
1 6 .3 8 4 M b it/s
0 1 64 12 5s
F ra m e S ig n al
sw iti_ 038.em f
Figure 24
Frame Signal Example
Figure 24 shows an example of a frame signal beginning with the rising edge of the 64th clock cycle with a length of 4 clock cycles. Further programming examples can be found
4.6.2
GPCLK as Clock Outputs
All 8 GPCLK lines can be configured as individual clock outputs with 8 kHz, 2.048 MHz, 4.096 MHz, 8.192 MHz, 16.384 MHz and for test purposes with the internal frequency or the input frequency of the analog PLL (APLL). All clock signals are generated from the analog PLL output frequency which is the internal frequency. The quality of all output frequency signals depends on the quality of the selected input PLL frequency.
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4.7
JTAG (Boundary Scan)
The SWITI provides a fully IEEE 1149.1 compatible boundary scan support consisting of: - a complete boundary scan chain - a Test Access Port controller (TAP controller) - five dedicated pins: TCK, TMS, TDI, TDO and a TRST to asynchronously reset the TAP controller - one 32-bit IDCODE register
4.7.1
Boundary Scan
All pins except power supply and crystal are included in the boundary scan. Depending on the pin functionality one (input), two (output, enable) or three (input, output, enable) boundary scan cells are provided. The maximum clock rate at pin TCK is 10 MHz.
4.7.2
Test-Access-Port (TAP)
The following signal pins allow the boundary scan test logic to be accessed: - TCK - Test Clock input to which a central BSc test clock is applied. This BSc test clock is independent of the system clock. Clock phases are derived from this clock for test sequence control. - TMS - Test Mode Select control input for which the desired status changes at the TAP controller by applying a certain level (0/1) caused by the rising edge of TCK. - TDI - Test Data Input whose data is inserted into the test logic with the rising edge of the TCK. - TDO - Test Data Output with tristate capability which is only active during the SHIFT-IR and SHIFT-DR controller state, and whose data is driven with the falling edge of TCK.
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4.7.3
TAP Controller
The Test Access Port (TAP) controller implements the state machine defined in the JTAG standard IEEE 1149.1. Transitions on the pin TMS cause the TAP controller to perform a state change. The possible instructions are listed in the following table. Table 14 Code 0000 0001 0100 0101 0110 0111 1111 TAP Controller Instructions Instruction EXTEST IDCODE HIGHZ INTEST CLAMP BYPASS Function External testing Reading ID code High impedance state of all boundary scan outputs Internal testing Reading outputs Bypass operation
SAMPLE/PRELOAD Snap-shot testing
The instruction length is four bit. EXTEST is used to verify the board interconnections. When the TAP controller is in the state "update DR", all output pins are updated with the falling edge of TCK. When it has entered state "capture DR" the levels of all input pins are latched with the rising edge of TCK. The in/out shifting of the scan vectors is typically done using the instruction SAMPLE/PRELOAD. INTEST supports internal chip testing. When the TAP controller is in the state "update DR", all inputs are updated internally with the falling edge of TCK. When it has entered state "capture DR" the levels of all outputs are latched with the rising edge of TCK. The in/out shifting of the scan vectors is typically done using the instruction SAMPLE/PRELOAD. SAMPLE/PRELOAD The SAMPLE/PRELOAD instruction enables all signal pins (inputs and outputs) to be sampled during operation (SAMPLE) and the result to be shifted out through the shift BSc register. The function of the internal logic is not influenced by this instruction. While shifting out, the BSc cells can be serially loaded at the same time with defined values through TDI (PRELOAD). The SAMPLE/PRELOAD instruction selects the boundary scan register in normal mode. In state CAPTURE-DR data is loaded into the boundary scan register with the rising edge of TCK. In state UPDATE-DR the contents of the boundary scan register are written into the second register stage of the boundary scan register. This data becomes effective at the outputs only if an instruction has been activated that sets the BSc register to test mode: e.g. EXTEST or CLAMP.
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PRELIMINARY IDCODE The 32-bit identification register is serially read out via TDO. It contains the version number (4 bits), the device code (16 bits) and the manufacturer code (11 bits). The LSB is fixed to '1'.. Description of Interfaces
Version xxxx
Device Code xxxx xxxx xxxx xxxx
Manufacturer Code xxxx xxxx xxx 1
Output --> TDO
Table 15 HTSI HTSI-L HTSI-XL CLAMP
Boundary Scan IDCODE Version 0010 0010 0010 Device Code Manufacture Code Bit0 1 1 1 0000 0000 0110 1101 0000 1000 001 0000 0000 0110 1110 0000 1000 001 0000 0000 0110 1111 0000 1000 001
The BSc register is in test mode. For the duration of the CLAMP instruction, the BYPASS register is selected so that a minimal shift path is created. During SHIFT-DR data can be shifted through the BYPASS register. The contents of the BSc register does not change during the UPDATE-DR state. HIGHZ The HIGHZ instruction disables all outputs if switched to high impedance state. The outputs are switched to high impedance in state UPDATE-IR. The outputs are redefined according to the next new instruction if another instruction has become active with UPDATE-IR. The selected test data register is the BYPASS register. BYPASS, a bit entering TDI is shifted to TDO after one TCK clock cycle, e.g. to skip testing of selected ICs on a printed circuit board.
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4.8
Identification Code via P Read Access
The SWITI offers two possibilities to read the identification code. - via the JTAG port as described in Chapter 4.7 - or via the processor interface After a hardware reset the identification code is stored in the General Purpose Interrupt Register (GPI) and can be read via the processor interface. The high nibble is the version number and the low nibble is equal to the low nibble of the device code shown in Table 16. For the 8-bit P interface configuration the first write access to the General Purpose Mask Register (GPM) will reset the register GPI to 00H. If the P interface is configured as a 16-bit interface the IDCODE can always be read from the GPI register, that means the GPI register will not be reset. The IDCODE for the P read access is shown in Table 16. Table 16 IDCODE via P Read Access 8-Bit IDCODE (MSB..LSB) Version HTSI HTSI-L HTSI-XL 0010 0010 0010 Device Code 1101 1110 1111
Note: The version number of the IDCODE register remains unchanged.
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5
Register Description
The register description gives information about all registers accessible via the microprocessor interface according to address, short name, access, reset value and value range.
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5.1
Table 17 Reg Name SPA ITSA DPA OTSA SCA GI1 GI2 CCMD CMD1 CMD2 MV ISTA1
Register Overview For 8-Bit Interface
Register Overview For 8-Bit Interface Access 8-bit Reset Address Value RD/WR RD/WR RD/WR RD/WR RD/WR RD/WR RD/WR RD/WR RD/WR RD/WR RD/WR RD 00H 01H 02H 03H 07H 04H 05H 06H 08H 0AH 0CH 0EH 10H 11H 12H 14H 15H 16H 18H 1AH 1BH 1CH 1EH 1FH 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 3DH 3FH FFH 00H 00H 00H FFH XXH XXH Comment Source Port Address Register Value range see Table 18 Input Time-Slot Address Register Value range see Table 19 Destination Port Address Register Value range see Table 18 Output Time-Slot Address Register Value range see Table 19 Subchannel Address Register Value range see Table 20 General Input Register 1 General Input Register 2 Connection Command Register Configuration Command Register 1 Configuration Command Register 2 Message Value Register Interrupt Status Register 1 Interrupt Error Status Register 1 Interrupt Error Status Register 2 Interrupt Mask Register 1 Interrupt Error Mask Register 1 Interrupt Error Mask Register 2 General Purpose Port Input Register General Purpose Port Output Register General Purpose Direction Register General Purpose Mask Register Time-Slot Value Register Configuration Register Page No. 61 61 62 62 62 63 65 66 68 74 78 78 79 80 81 82 83 83 84 84 84 85 85 89
IESTA1 RD IESTA2 RD INTM1 RD/WR INTEM1 RD/WR INTEM2 RD/WR GPPI GPPO GPD GPM GPI TSV CON RD WR RD/WR RD/WR RD RD RD
IDCODE General Purpose Interrupt Register
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PRELIMINARY Table 18 Value Range for SPA/DPA Value Range Bit4..0 15..0 31..0 31..0 Register Description
Addressed Lines Local-Bus input lines (H-Mode) Local-Bus input lines (M-Mode) H-Bus lines (H-Mode)
Table 19 Data Rate 2.048 Mbit/s 4.096 Mbit/s 8.192 Mbit/s
Value Range for ITSA/OTSA Range Bit7..0 31..0 63..0 127..0
16.384 Mbit/s 255..0
Table 20 Mode
Value Range for SCA Range
1-bit switching 0..7 for ISCA0..2; 0..7 for OSCA0..2 2-bit switching 0..3 for ISCA0..1; 0..3 for OSCA0..1 4-bit switching 0..1 for ISCA0; 0..1 for OSCA0
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5.2
Detailed Register Description For 8-bit Interface
RD/WR
Source Port Address Register Reset value: 00H
7 SPA BT 6 0 5 0 4
Address: 00H
3 PA3
2 PA2
1 PA1
0 PA0
PA4
BT
Bus Type (must be set to logical "0" in M-mode) 0 = Local Bus 1 = H-bus
PA4..0 Port Address
Input Time-Slot Address Register Reset value: 00H
7 ITSA TSA7 6 TSA6 5 TSA5 4
RD/WR
Address: 01H
3 TSA3
2 TSA2
1 TSA1
0 TSA0
TSA4
TSA7..0 Time-Slot Address
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PRELIMINARY Register Description RD/WR
Destination Port Address Register Reset value: 00H
7 DPA BT 6 0 5 0 4
Address: 02H
3 PA3
2 PA2
1 PA1
0 PA0
PA4
BT
Bus Type (must be set to logical "0" in M-mode) 0 = Local Bus 1 = H-bus
PA4..0 Port Address
Output Time-Slot Address Register Reset value: 00H
7 OTSA TSA7 6 TSA6 5 TSA5 4
RD/WR
Address: 03H
3 TSA3
2 TSA2
1 TSA1
0 TSA0
TSA4
TSA7..0 Time-Slot Address
Subchannel Address Register Reset value: 00H
7 SCA 0 6 0 5 4
RD/WR
Address: 07H
3
2
1
0
OSCA2 OSCA1 OSCA0 ISCA2 ISCA1 ISCA0
OSCA2..0 Output Subchannel Address ISCA2..0 Input Subchannel Address
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PRELIMINARY Register Description RD/WR
General Input Register 1 Reset value: 00H
7 GI1 GV7 6 GV6 5 GV5 4
Address: 04H
3 GV3
2 GV2
1 GV1
0 GV0
GV4
GV7..0 General Value In case of a PLL Reference (main and secondary) Selection Command (CMD1) the content of this register is interpreted as follows: GV2..0 Clock Frequency 000 = 8 kHz 001 = 512 kHz 010 = 1.536 MHz 011 = 1.544 MHz 100 = 2.048 MHz 101 = 4.096 MHz 110 = 8.192 MHz 111 = 16.384 MHz
In case of a CT_NETREF_1/2 Output Selection Command (CMD1) the content of this register is interpreted as follows: GV1..0 Output CT_NETREF_1/2 Clock Frequency 00 = 8 kHz 01 = 512 kHz 10 = 2.048 MHz
Preliminary Data Sheet
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PRELIMINARY Register Description
In case of a Bit Shift Command (CMD1) the content of this register is interpreted as follows: GV4 Bit shift value (only for input lines) 0 = bit shift applies before PFS rising edge 1 = bit shift applies after PFS rising edge GV3..1 Bit shift value (range: 7 to 0) GV0 Edge Control Bit (half clock shift) 0 = data transmit with rising edge and is sampled with falling edge 1 = data transmit with falling edge and is sampled with rising edge
In case of the GPCLK as Frame Signal Command (CMD2) the content of this register is interpreted as follows: GV7..2 Offset within the PFS frame in number of 16.384 MHz clock cycles (lower 6 bits; refer to GI2 for the upper part) GV1 Edge Control Bit 0 = data changes with rising edge and is sampled with falling edge 1 = data changes with falling edge and is sampled with rising edge GV0 Reserved
In case of the GPCLK as Clock Signal Command (CMD2) the content of this register is interpreted as follows: GV2..0 Output Frequency for the selected line 000 = 8 kHz 001 = 2.048 MHz 010 = 4.096 MHz 011 = 8.192 MHz 100 = 16.384 MHz 101 = Input Analog PLL (2.048 MHz) 110 = Internal Frequency (49.152 MHz)
Preliminary Data Sheet
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PRELIMINARY Register Description RD/WR
General Input Register 2 Reset value: 00H
7 GI2 GV7 6 GV6 5 GV5 4
Address: 05H
3 GV3
2 GV2
1 GV1
0 GV0
GV4
GV7..0 General Value
In case of the GPCLK as Frame Signal Command (CMD2) the content of this register is interpreted as follows: GV7..5 Width of the pulse in number of 16.384 MHz clock cycles from 1 to 8 i.e. GV7..5 = 000 => 1 clock cycle, GV7..5 = 010 => 3 clock cycles GV4..0 Offset within the PFS frame in number of 16.384 MHz clock cycles (upper 5 bits; refer to GI1 for the lower part)
Preliminary Data Sheet
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PRELIMINARY Register Description RD/WR
Connection Command Register Reset value: 00H
7 CCMD I3 6 I2 5 I1 4 I0
Address: 06H
3 CC3
2 CC2
1 CC1
0 CC0
CC3..0 Command Code 0000 = no operation at all 0001 = Constant Delay Connection Command (incl. Broadcast Connection) (SPA, ITSA, DPA, OTSA, SCA are considered) I1..0 Subchannel Mode 00 = 01 = 10 = 11 = 8-bit wide time-slots 4-bit wide time-slots 2-bit wide time-slots 1-bit wide time-slots
0010 = Minimum Delay Connection Command (incl. Broadcast Connection) (SPA, ITSA, DPA, OTSA are considered) 0011 = Send Message Command (always Constant Delay) (DPA, OTSA, MV are considered) 0100 = Stop Message Command (DPA, OTSA are considered) 0101 = Disconnect Command (SPA, ITSA, DPA, OTSA, SCA are considered) I1..0 see I1..0 of Constant Delay Connection Command (incl. Broadcast Connection)
0110 = Disconnect Part of Broadcast Command (SPA, ITSA, DPA, OTSA, SCA are considered) I1..0 see I1..0 of Constant Delay Connection Command (incl. Broadcast Connection)
0111 = Multipoint Connect Command (SPA, ITSA, DPA, OTSA are considered) I0 Multipoint MODE 0= 1= logical OR connection logical AND connection
Preliminary Data Sheet
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PRELIMINARY 1000 = Disconnect All Command 1001 = Bidirectional Connect Command (SPA, ITSA, DPA, OTSA are considered) I0 Delay MODE 0= 1= I0 Minimum Delay Constant Delay Register Description
1010 = Memory Dump (Connection and Data Memory) Memory Dump 0= 1= disable enable
Preliminary Data Sheet
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PRELIMINARY Register Description RD/WR
Configuration Command Register 1 Reset value: 00H
7 CMD1 I3 6 I2 5 I1 4 I0
Address: 08H
3 CC3
2 CC2
1 CC1
0 CC0
CC3..0 Command Code 0000 = no operation 0001 = Set as H.100/H.110 Master/Slave (HTSI H-Mode) Must be programmed only after PLL input initialization and/or H.1x0 fallback command I0 Mode Information 0= 1= Slave mode Master mode
0010 = PLL Primary Reference Selection Command for Master (GI1 is considered to set the frequency) I3..0 Synchronization Information 0000 = no synchronization = internal oscillator (default) 0001 = synchronizes the PLL to PFS (only M-Mode) 0010 = synchronizes the PLL to PDC (only M-Mode) 0011 = synchronizes the PLL to CT_NETREF_1 (only Hmode) 0100 = synchronizes the PLL to CT_NETREF_2 (only Hmode) 0101 = synchronizes the PLL to NTWK_1 0110 = synchronizes the PLL to NTWK_2 0111 = synchronizes the PLL to CT_A (CT_C8_A and CT_FRAME_A) (only H-mode, GI1 isn't considered) 1000 = synchronizes the PLL to CT_B (CT_C8_B and CT_FRAME_B) (only H-mode, GI1 isn't considered) 1001 = not used 1010 = not used 1011 = synchronizes the PLL to FR_COMP (only H-mode) 1100 = synchronizes the PLL to SCLK (only H-mode)
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PRELIMINARY Register Description 1101 = synchronizes the PLL to C2 (only H-mode) 1110 = synchronizes the PLL to C4 (only H-mode) 1111 = synchronizes the PLL to C16 (only H-mode) 0011 = PLL Secondary Reference Selection Command for Master (only Hmode) (GI1 is considered to set the frequency) I3..0 Synchronization Information 0000 = no synchronization = internal oscillator (default) 0001 = synchronizes the PLL to CT_NETREF_1 0010 = synchronizes the PLL to CT_NETREF_2 0011 = synchronizes the PLL to NTWK_1 0100 = synchronizes the PLL to NTWK_2 0101 = synchronizes the PLL to CT_C8_A 0110 = synchronizes the PLL to CT_C8_B 0111 = synchronizes the PLL to CT_FRAME_A 1000 = synchronizes the PLL to CT_FRAME_B 1001 = synchronizes the PLL to FR_COMP 1010 = synchronizes the PLL to SCLK 1011 = synchronizes the PLL to SCLKx2 1100 = synchronizes the PLL to C2 1101 = synchronizes the PLL to C4 1110 = synchronizes the PLL to C16 1111= start special configuration register programming 0100 = PLL Source Selection Command. - Slave Path (only H-mode) I3..0 Source/Frequency Information 0000 = not used 0001 0010 0011 0100 0101 0110 0111
Preliminary Data Sheet
not used not used not used not used CT_A (CT_C8_A and CT_FRAME_A) CT_B (CT_C8_B and CT_FRAME_B) SCLK = 2.048 MHz and FR_COMP
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PRELIMINARY 1000 1001 1010 1011 1100 1111 I1..0 Register Description SCLK = 4.096 MHz and FR_COMP SCLK = 8.192 MHz and FR_COMP C2 = 2.048 MHz and FR_COMP C4 = 4.096 MHz and FR_COMP C16 = 16.384 MHz and FR_COMP write special configuration register (GI1 is considered)
0101 = H.100/H.110 Clock Output Selection Command (only H-mode) Activation Information 00 = 01 = 10 = I3..2 disable CT_FRAME and CT_C8 (default) enable CT_FRAME_A and CT_C8_A enable CT_FRAME_B and CT_C8_B
Not used must be set to '0'
0110 = PCM Clock Input/Output Selection Command (Default: PFS and PDC inactive) I2..0 Frequency Information 000 = 001 = 010 = 011 = 100 = I3 0= 1= I0 reserved enable PFS and PDC = 2.048 MHz enable PFS and PDC = 4.096 MHz enable PFS and PDC = 8.192 MHz enable PFS and PDC = 16.384 MHz PFS and PDC as Input PFS and PDC as Output
Direction Information
0111 = Compatibility Clock Output Selection Command (only H-mode) MVIP-90 Activation Information 0= 1= I1 0= 1= I3..2 00 = disable MVIP-90 - C2, C4, FR_COMP (default) enable MVIP-90 - C2, C4, FR_COMP disable H-MVIP - C2, C4, C16, FR_COMP (default) enable H-MVIP - C2, C4, C16, FR_COMP disable SCbus - SCLK, SCLKx2, Fsync* (default)
H-MVIP Activation Information
SCbus Activation/Frequency Information
Preliminary Data Sheet
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PRELIMINARY 01 = 10 = 11 = I0 enable SCbus - 2.048 MHz enable SCbus - 4.096 MHz enable SCbus - 8.192 MHz Register Description
1000 = CT_NETREF_1 Output Selection Command (only H-mode) Inversion Information 0= 1= I3..1 000 = 001 = 010 = 011 = 100 = normal CT_NETREF_1 output invert CT_NETREF_1 output disable CT_NETREF_1 (default) enable CT_NETREF_1 - source NTWK_1 enable CT_NETREF_1 - source NTWK_2 enable CT_NETREF_1 - source NETREF_2 enable CT_NETREF_1 - source internal oscillator (GI1 is considered to set the output frequency)
Activation Information
1001 = CT_NETREF_2 Output Selection Command (only H-mode) I0 Inversion Information 0= 1= I3..1 000 = 001 = 010 = 011 = 100 = normal CT_NETREF_2 output invert CT_NETREF_2 output disable CT_NETREF_2 (default) enable CT_NETREF_2 - source NTWK_1 enable CT_NETREF_2 - source NTWK_2 enable CT_NETREF_2 - source NETREF_1 enable CT_NETREF_2 - source internal oscillator (GI1 is considered to set the output frequency)
Activation Information
1010 = H.100/H.110 Fallback Mechanism I1..0 PLL Source (only H-mode) 00 = 01 = 10 = 11 = disable (default) from PLL Main Ref. to Secondary Ref. (If SWITI is Primary "A" Master in the system) from PLL Main Ref. to Secondary Ref. (If SWITI is Secondary "B" Master in the system) from A clock to B clock (Slave)
Preliminary Data Sheet
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PRELIMINARY I2 Register Description Re-Fallback Activation Information for Primary Master (only H-mode) 0= 1= I3 0= 1= disable automatic switch back to main ref. (default) enable automatic switch back to main ref. disable (default after reset) enable Must be set for H.1x0 slave
PLL Phase Alignment (Please see description, Chapter 3.4.4)
1011 = Set Bit Rate Command Local Bus (Default for all lines = 2.048 Mbit/s) I1..0 Base Bit Rate Information 00 = 01 = 10 = 11 = I2 0= 1= I3 0= 1= 2.048 Mbit/s 4.096 Mbit/s 8.192 Mbit/s 16.384 Mbit/s no effect set rate of local input lines (SPA is considered) no effect set rate of local output lines (DPA is considered)
Destination Information
Destination Information
1100 = Set Bit Rate Command H.100/H.110 and Interoperability Bussystems (Default for all lines = 2.048 Mbit/s) I1..0 Base Bit Rate Information 00 = 01 = 10 = 11 = I0 2.048 Mbit/s (SPA is considered) 4.096 Mbit/s (SPA is considered) 8.192 Mbit/s (SPA is considered) set all lines to 8.192 Mbit/s
1101 = Read Time-Slot Command Destination Information 0= 1= read input time-slots(SPA, ITSA are considered) read output time-slots(DPA, OTSA are considered)
Preliminary Data Sheet
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PRELIMINARY Register Description
1110 = Stream to Stream Switch Command (SPA, DPA are considered) (The value for SPA and DPA can not be equal) The command affects H-Bus only and depends on the selected bit rate I1..0 Connection (see Figure 10 on page 28) depends on the selected bit for every line 00 = 01 = 10 = 11 = I2 0= 1= I3 0= 1= Mode 0 Mode 1 Mode 2 Mode 3 release current stream to stream connection establish current stream to stream connection reserved release all programmed stream to stream connections
Connection Information
Destination Information
1111 = Bit Shift Command (GI1 is considered to set shift value) (Default: Bit Shift is inactive) I1..0 Direction Control 00 = 01 = 10 = 11 = Set shift value for input line (SPA is considered) Set shift value for all input lines Set shift value for all output lines Set shift value for all lines (input and output)
Preliminary Data Sheet
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PRELIMINARY Register Description RD/WR
Configuration Command Register 2 Reset value: 00H
7 CMD2 I3 6 I2 5 I1 4 I0
Address: 0AH
3 CC3
2 CC2
1 CC1
0 CC0
CC3..0 Command Code 0000 = no operation at all 0001 = External Frequency I0 Set External Frequency (Must be programmed first) 0= 1= I1 0= 1= 32.768 MHz 16.384 MHz disable (and turn off "enable" status temporarily if fallback has occurred) enable
Fallback to Oscillator
If "Fallback to Oscillator" is enabled and a fallback has occurred, the corresponding failure is indicated in the IESTA1 and/or IESTA2 registers. For all clock failures, the PLL bit ("PLL Source Failure Indication", IESTA2 register) as well as the clock source related bit (in IESTA1 or IESTA2 register) will be set to "1". With the clock valid again the previously changed bits in IESTA1 and/or IESTA2 are set back to "0", the fallback must be disabled (CMD2=01H/11H) for a few cycles and enabled again thereafter. I2 APLLs parameters 0= 1= default start APLL with improved parameters
The command CMD2=41H or CMD2=51H to start the APLL with improved parameters must only be issued only once after Power Up 0010 = Parallel Mode (local bus only) Set the first 8 local bus input lines as 8 parallel input lines and set the first 8 local bus output lines as 8 parallel output lines. I0 Set Parallel Mode
Preliminary Data Sheet
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PRELIMINARY 0= 1= I1..0 disable enable Register Description
0011 = IREQ Pin Command Set IREQ Pin (Default: IREQ is inactive) 00 = 01 = 10 = I2 IREQ is active low IREQ is active high IREQ as open-drain pin
Set Interrupt Time-Out Counter Set the inactive time between two consecutive interrupts 0= 1= disable = 20 ns enable = 300 ns
0100 = PCM and H.1x0 Standby Command I0 Set PCM to High Impedance 0= 1= I1 0= 1= I2 I3 outputs are tristated (default) outputs are enabled I/O's are tristated (default) I/Os are enabled
Set H.1x0 to High Impedance (only H-mode)
not used must be set to '0' Internal PCM Clock Synchronization 0= 1= Must be set in PCM clock master mode Must be set in PCM clock slave mode
0101 = Loop Command I0 Set PCM-PCM Loop 0= 1= I1 0= 1= disable (default) enable disable (default) enable
Set H.100/H.110 Loop (only H-mode)
0110 = GPCLK as Frame Signal Command (GI1, GI2 are considered) (Default: All GPCLK's are tristated) I2..0
Preliminary Data Sheet
GPCLK Line (7..0)
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PRELIMINARY I3 Invert Mode 0= 1= frame signal is high active frame signal is low active Register Description
0111 = GPCLK as Clock Signal Command (GI1 is considered to set the frequency) (Default: All GPCLK's are tristated) I2..0 GPCLK Line (7..0) 1000 = Set Range of Data Rate Command To avoid loss of data this command should be issued only once after reset. If the range of data rate is changed later on, loss of data must be expected for up to four frames. (Additionally for the H-mode the 8.192 Mbit/s bit must be set.) I3..0 Range Select To specify the range the min and max codes have to be logical OR combined. 0001 = 2.048 Mbit/s (default) 0010 = 4.096 Mbit/s 0100 = 8.192 Mbit/s 1000 = 16.384 Mbit/s 1001 = Read Configuration I3..0 Select Configuration Command 0000 = Master/Slave Configuration (only H-mode) 0001 = PLL Primary Master Source 0010 = PLL Secondary Master Source (only H-mode) 0011 = PLL Source (Slave Path) (only H-mode) 0100 = Clock Output Selection for H.1x0 (only H-mode) 0101 = Clock Output Selection for PCM 0110 = Clock Output Selection for Interoperability Signals (only H-mode) 0111 = Output Selection for CT_NETREF_1 (only H-mode) 1000 = Output Selection for CT_NETREF_2 (only H-mode) 1001 = Fallback Mechanism and Phase Alignment 1010 = External Input Frequency 1011 = Parallel Mode
Preliminary Data Sheet
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PRELIMINARY 1100 = IREQ Pin 1101 = H.1x0/PCM Standby 1110 = Loop 1111 = Range of Data Rate 1010 = Read GPCLK Configuration I2..0 I0 GPCLK Line 7..0 Destination Information 0= 1= Read Data Rate of Input Line (SPA is considered) Read Data Rate of Output Line (DPA is considered) 1011 = Read PCM Line Configuration Register Description
1100 = Read H.1x0 Line Configuration (SPA is considered) (only H-mode) 1101 = Read Bit Shift Configuration I0 Destination Information 0= 1= 1110 = Reserved 1111 = Software Reset I0 Set Software Reset 0= 1= Deactivate Software Reset (default) Activate Software Reset Shift Value for Input Line (SPA is considered) Shift Value for all Output Lines
Preliminary Data Sheet
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PRELIMINARY Register Description RD/WR
Message Value Register Reset value: 00H
7 MV MV7 6 MV6 5 MV5 4
Address: 0CH
3 MV3
2 MV2
1 MV1
0 MV0
MV4
MV7..0 Message Value
Interrupt Status Register 1 Reset value: 00H
7 ISTA1 APLL 6 STR 5 ER2 4
RD
Address: 0EH
3 GPIO
2 TSA
1 NFC
0 RDY
ER1
APLL APLL lock indication 0 = PLL is not locked = bypassed 1 = PLL is locked STR Stream to Stream Indication 0 = no stream to stream connection is set 1 = stream to stream connections are set ER2 Error2 Interrupt Change Indication (not active in 16-bit mode) 0 = no change detected in the Interrupt Error Status Register 2 (IESTA2) 1 = change detected in the Interrupt Error Status Register 2 (IESTA2) ER1 Error1 Interrupt Change Indication 0 = no change detected in the Interrupt Error Status Register 1 (IESTA1) 1 = change detected in the Interrupt Error Status Register 1 (IESTA1) GPIO General Purpose Change Indication 0 = no change according to GP port inputs detected 1 = at least one change according to GP port inputs detected TSA Time-Slot Arrived Indication 0 = there is no new time-slot value in the register TSV
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PRELIMINARY 1 = there is a new time-slot value in the register TSV NFC No Further Connections Indication 0 = establishing of connections is possible 1 = the maximum amount of connections is reached RDY Ready Indication 0 = CCMD is not ready to be written to 1 = CCMD is ready to be written to Register Description
Interrupt Error Status Register 1 Reset value: 00H
7 IESTA1 0 6 0 5 NR2 4
RD
Address: 10H
3 CTB
2 CTA
1 NW2
0 NW1
NR1
NR2 CT_NETREF_2 Failure Indication NR1 CT_NETREF_1 Failure Indication CTB CT_C8_B or CT_FRAME_B Failure Indication CTA CT_C8_A or CT_FRAME_A Failure Indication NW2 NTWK_2 Failure Indication NW1 NTWK_1 Failure Indication for all these status bits the values can be
0 = no failure detected 1 = failure detected
Preliminary Data Sheet
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PRELIMINARY Register Description RD
Interrupt Error Status Register 2 Reset value: 00H
7 IESTA2 CON 6 PLL 5 FRC 4
Address: 11H
3 SC
2 C2
1 C4
0 C16/S
SC2
CON PLL FRC SC2 SC C2 C4 C16/S C16/S
Connection Memory Error/Overflow Indication PLL Source Failure Indication FR_COMP Failure Indication SCLK2 Failure Indication SCLK Failure Indication C2 Failure Indication C4 Failure Indication C16 Failure Indication Secondary Reference Failure Indication (only in master mode)
for all these status bits the values can be
0 = no failure detected 1 = failure detected
Preliminary Data Sheet
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PRELIMINARY Register Description RD/WR
Interrupt Mask Register 1 Reset value: 3DH
7 INTM1 0 6 0 5 ER2 4
Address: 12H
3 GPIO
2 TSA
1 0
0 RDY
ER1
ER2
Error2 Interrupt Change Indication Mask (not active in 16-bit mode) 0 = Do not mask the Change Indication Bit 1 = Mask the Change Indication Bit
ER1
Error1 Interrupt Change Indication Mask 0 = Do not mask the Change Indication Bit 1 = Mask the Change Indication Bit
GPIO General Purpose Change Indication Mask 0 = Do not mask the Change Indication Bit 1 = Mask the Change Indication Bit TSA Time-Slot Arrived Indication Mask 0 = Do not mask the Time-Slot Arrived Indication Bit 1 = Mask the Time-Slot Arrived Indication Bit RDY Ready Indication Mask 0 = Do not mask the Ready Indication Bit 1 = Mask the Ready Indication Bit Mask = Disable the interrupt
Preliminary Data Sheet
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PRELIMINARY Register Description RD/WR
Interrupt Error Mask Register 1 Reset value: 3FH
7 INTEM1 0 6 0 5 NR2 4
Address: 14H
3 CTB
2 CTA
1 NW2
0 NW1
NR1
NR2 CT_NETREF_2 Failure Indication Mask NR1 CT_NETREF_1 Failure Indication Mask CTB CT_C8_B or CT_FRAME_B Failure Indication Mask CTA CT_C8_A or CT_FRAME_A Failure Indication Mask NW2 NTWK_2 Failure Indication Mask NW1 NTWK_1 Failure Indication Mask for all these status bits the values can be
0 = Do not mask this interrupt 1 = Mask this interrupt Mask = Disable the interrupt
Preliminary Data Sheet
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PRELIMINARY Register Description RD/WR
Interrupt Error Mask Register 2 Reset value: FFH
7 INTEM2 CON 6 PLL 5 FRC 4
Address: 15H
3 SC
2 C2
1 C4
0 C16/S
SC2
CON PLL FRC SC2 SC C2 C4
Connection Memory Overflow Indication Mask PLL Source Failure Indication Mask FR_COMP Failure Indication Mask SCLK2 Failure Indication Mask SCLK Failure Indication Mask C2 Failure Indication Mask C4 Failure Indication Mask
C16/S C16 Failure Indication Mask C16/S Secondary Reference Failure Indication Mask (only in master mode) For all these status bits the values can be
0 = Do not mask this interrupt 1= Mask this interrupt Mask = Disable the interrupt
General Purpose Port Input Register RD Reset value: 00H
7 GPPI GPB7 6 GPB6 5 GPB5 4 GPB4 3 GPB3 2 GPB2 1 GPB1
Address: 16H
0 GPB0
GPB7..0 General Purpose Bits
Preliminary Data Sheet
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PRELIMINARY Register Description
General Purpose Port Output RegisterWR Reset value: 00H
7 GPPO GPB7 6 GPB6 5 GPB5 4 GPB4 3 GPB3 2 GPB2 1 GPB1
Address: 18H
0 GPB0
GPB7..0 General Purpose Bits
General Purpose Direction Register Reset value: 00H
7 GPD DC7 6 DC6 5 DC5 4
RD/WR
Address: 1AH
3 DC3
2 DC2
1 DC1
0 DC0
DC4
DC7..0 Direction Control 0 = set line as input 1 = set line as output
General Purpose Mask Register Reset value: FFH
7 GPM IM7 6 IM6 5 IM5 4
RD/WR
Address: 1BH
3 IM3
2 IM2
1 IM1
0 IM0
IM4
IM7..0 GPIO Interrupt Mask (bit 0 for line 0, bit 1 for line 1 ..) 0 = enable change detection 1 = disable change detection
Preliminary Data Sheet
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PRELIMINARY Register Description RD
General Purpose Interrupt Register Reset value: IDCODE
7 GPI IND7 6 IND6 5 IND5 4
Address: 1CH
3 IND3
2 IND2
1 IND1
0 IND0
IND4
IND7..0 GPIO Interrupt Indication (bit 0 for line 0, bit 1 for line 1 ..) 0 = no change detected 1 = at least one change detected on this line
Time-Slot Value Register Reset value: XXH
7 TSV TSV7 6 TSV6 5 TSV5 4
RD
Address: 1EH
3 TSV3
2 TSV2
1 TSV1
0 TSV0
TSV4
For the Read Time-Slot Value Command the content of the TSV register is interpreted as: TSV7..0 Time-Slot Value
For the Read Configuration Command the content of the TSV register is interpreted as: Master/Slave Configuration only H-mode (page 68) TSV0 0= 1= Slave Master
PLL Primary Master Configuration TSV3..0 See I3..0 from PLL Primary Master Reference Selection Command (page 68) TSV6..4 000 = 001 = 010 = 8 kHz 512 kHz 1.536 MHz
Preliminary Data Sheet
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PRELIMINARY 011 = 100 = 101 = 110 = 111 = 1.544 MHz 2.048 MHz 4.096 MHz 8.192 MHz 16.384 MHz Register Description
PLL Secondary Master Configuration TSV3..0 See I3..0 from PLL Secondary Master Reference Selection Command (page 69) TSV6..4 000 = 001 = 010 = 011 = 100 = 101 = 110 = 111 = 8 kHz 512 kHz 1.536 MHz 1.544 MHz 2.048 MHz 4.096 MHz 8.192 MHz 16.384 MHz
PLL Source Selection TSV3..0 See I3..0 from PLL Source Selection Command (page 69) H.1x0 Clock Output Selection only H-mode TSV1..0 See I1..0 from H.1x0 Clock Output Selection Command (page 70) PCM Clock Output Selection TSV3..0 See I3..0 from PCM Clock Output Selection Command (page 70) Compatibility Clock Output Selection only H-mode TSV3..0 See I3..0 from Compatibility Clock Output Selection Command (page 70) CT_NETREF_1 Output Selection only H-mode TSV3..0 See I3..0 from CT_NETREF_1 Output Selection Command (page 71) TSV5..4 Use TSV5..4, if TSV3..0 = 100x 00 = 01 = 8 kHz 512 kHz
Preliminary Data Sheet
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PRELIMINARY 10 = 2.048 MHz Register Description
CT_NETREF_2 Output Selection only H-mode TSV3..0 See I3..0 from CT_NETREF_2 Output Selection Command (page 71) TSV5..4 Use TSV5..4, if TSV3..0 = 100x 00 = 01 = 10 = 8 kHz 512 kHz 2.048 MHz
H.1x0 Fallback Mechanism and Phase Alignment TSV3..0 See I3..0 from H.1x0 Fallback Mechanism and Phase Alignment Command (page 71) External Frequency TSV0 TSV0 IREQ Pin TSV2..0 See I1..0 from Set IREQ Pin Command (page 75) H.1x0/PCM Standby TSV1..0 See I0 from Set H.1x0/PCM Standby Command (page 75) Loop TSV1..0 See I1..0 from Loop Command (page 75) Range of Data Rate TSV3..0 See I3..0 from Set Range of Data Rate Command (page 76) See I0 from Set External Frequency Command (page 74) See I0 from Set Parallel Mode Command (page 74) Parallel Mode
Preliminary Data Sheet
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PRELIMINARY Register Description
For the Read GPCLK Configuration Command the content of the TSV register is interpreted as: TSV0 0= 1= TSV3..1 000 = 001 = 010 = 011 = 100 = 101 = 110 = TSV1 0= 1= GPCLK Line as Clock Signal GPCLK Line as Frame Signal 8 kHz 2.048 MHz 4.096 MHz 8.192 MHz 16.384 MHz Input Analog PLL Internal Frequency Rising Edge Falling Edge
GPCLK Line as Clock Signal
GPCLK Line as Frame Signal
TSV7..2 Offset within the PFS frame in number of 16.384 MHz clock cycles (lower 6 bits; refer to CON for the upper part)
For the Read PCM and H.1x0 Line Configuration Command the content of the TSV register is interpreted as: TSV1..0 00 = 01 = 10 = 11 = 2.048 MBit/s 4.096 MBit/s 8.192 MBit/s 16.384 MBit/s (only for PCM)
Preliminary Data Sheet
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PRELIMINARY Register Description
In case of the Read Bit Shift Configuration Command the content of the TSV register is interpreted as: TSV0 Edge Control 0= 1= TSV4 Rising Edge Falling Edge
TSV3..1 Bit Shift Value (Range: 7 to 0) Byte Shift Value (only for input lines) 0= 1= bit shift applies to byte before PFS rising edge bit shift applies to byte before PFS falling edge
Configuration Register Reset value: XXH
7 CON CON7 6 CON6 5 CON5 4
RD
Address: 1FH
3 CON3
2 CON2
1 CON1
0 CON0
CON4
For the Memory Dump Command (CCMD) the content of the CON register is: CON7..0 Connection and Data Memory
For the Read GPCLK Configuration Command the content of the CON register is: CON7..5 Width of the pulse in number of 16.384 MHz clock cycles from 1 to 8 i.e. CON7..5 = 000 => 1 clock cycle, CON7..5 = 010 => 3 clock cycles CON4..0 Offset within the PFS frame in number of 16.384 MHz clock cycles (upper 5 bits; refer to TSV for the lower part)
Preliminary Data Sheet
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PRELIMINARY Register Description
5.3
Table 21
Register Overview For 16-Bit Interface
Register Overview For 16-Bit Interface Comment Source Address Register Destination Address Register General Input Register Connection Command Register 16-bit Configuration Command Register 1 This is a 8-bit register Configuration Command Register 2 This is a 8-bit register Message Value Register This is a 8-bit register Interrupt Status Register 1 This is a 8-bit register Interrupt Error Status Register Interrupt Mask Register This is a 8-bit register Interrupt Error Mask Register Page No. 91 91 92 92 68 74 78 78 93 81 93 94 94
Reg Access Address Reset Name Value SA DA GI CC16 RD/WR RD/WR RD/WR RD/WR 00H 02H 04H 06H 08H 0AH 0CH 0EH 10H 12H 14H 1CH 1EH 0000H 0000H 0000H 0000H 00H 00H 00H 00H 0000H 3DH FF3FH
CMD1 RD/WR CMD2 RD/WR MV ISTA1 IESTA RD/WR RD RD
INTM1 RD/WR INTEM RD/WR IDC TSVC RD RD
IDCODE IDCODE Register This is a 8-bit register XXXXH Time-Slot Value / Configuration Register
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PRELIMINARY Register Description
5.4
Detailed Register Description For 16-Bit Interface
RD/WR Address: 00H
Source Address Register Reset value: 0000H 15 TSA7 SA 7 BT 6 0 5 0 14 TSA6 13 TSA5
12 TSA4 4 PA4
11 TSA3 3 PA3
10 TSA2 2 PA2
9 TSA1 1 PA1
8 TSA0 0 PA0
High Low
See Input Time-Slot Address Register on page 61 See Source Port Address Register on page 61
Destination Address Register Reset value: 0000H 15 TSA7 DA 7 BT 6 0 5 0 14 TSA6 13 TSA5
RD/WR
Address: 02H
12 TSA4 4 PA4
11 TSA3 3 PA3
10 TSA2 2 PA2
9 TSA1 1 PA1
8 TSA0 0 PA0
High Low
See Output Time-Slot Address Register on page 62 See Destination Port Address Register on page 62
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PRELIMINARY General Input Register Reset value: 0000H 15 GV15 GI 7 GV7 6 GV6 5 GV5 4 GV4 3 GV3 2 GV2 1 GV1 0 GV0 14 GV14 13 GV13 12 GV12 11 GV11 10 GV10 9 GV9 8 GV8 RD/WR Register Description Address: 04H
GV15..0 General Value GV15..8 See General Input Register 2 on page 65 GV7..0 See General Input Register 1 on page 63
Connection Command Register 16-bit Reset value: 0000H 15 0 CC16 7 I3 6 I2 5 I1 4 I0 14 0 13 12
RD/WR
Address: 06H
11
10 ISCA2 2 CC2
9 ISCA1 1 CC1
8 ISCA0 0 CC0
OSCA2 OSCA1 OSCA0 3 CC3
High Low
See Subchannel Address Register on page 62 See Connection Command Register on page 66
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PRELIMINARY Interrupt Error Status Register Reset value: 0000H 15 CON IESTA 7 0 6 0 5 NR2 4 NR1 3 CTB 2 CTA 1 NW2 0 NW1 14 PLL 13 FRC 12 SC2 11 SC 10 C2 9 C4 8 C16/S RD Register Description Address: 10H
High See Interrupt Error Status Register 2 on page 80 Low See Interrupt Error Status Register 1 on page 79
Interrupt Error Mask Register Reset value: FF3FH 15 CON INTEM 7 0 6 0 5 NR2 14 PLL 13 FRC
RD/WR
Address: 14H
12 SC2 4 NR1
11 SC 3 CTB
10 C2 2 CTA
9 C4 1 NW2
8 C16/S 0 NW1
High See Interrupt Error Mask Register 2 on page 83 Low See Interrupt Error Mask Register 1 on page 82
Preliminary Data Sheet
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PRELIMINARY Register Description RD
IDCODE Register Reset value: IDCODE
7 IDC IDC7 6 IDC6 5 IDC5 4
Address: 1CH
3 IDC3
2 IDC2
1 IDC1
0 IDC0
IDC4
IDC7..0 IDCODE refer to Table 16 Time-Slot Value / Configuration RegisterRD Reset value: XXXXH 15
TSVC15
Address: 1EH
14
TSVC14
13
TSVC13
12
TSVC12
11
TSVC11
10
TSVC10
9
TSVC9
8
TSVC8
TSVC 7
TSVC7
6
TSVC6
5
TSVC5
4
TSVC4
3
TSVC3
2
TSVC2
1
TSVC1
0
TSVC0
TSVC15..8 Configuration and Connection Data Memory (refer to page 89) TSVC7..0 Time-Slot Value (refer to page 85)
Preliminary Data Sheet
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PRELIMINARY Programming the Device
6
Programming the Device
The register set consists of parameter registers (SPA, ITSA, SCA, DPA, OTSA, GI1..), command registers (CCMD, CMD1, CMD2) and status registers (ISTA1, IESTA1, IESTA2). Please note that some bits contained in the register ISTA1 (Interrupt Status Register 1) do not generate any interrupt, for more details see the paragraph Chapter 6.2. Before issuing a command the parameter registers have to be written accordingly. A connection command can only be issued if the connection command register is ready to be written to (see Figure 25). The connection command register status is shown with the RDY bit in the ISTA1 register. A detailed description for the read and write access to the command registers can be found in Chapter 6.1.
co m m a n d re g iste r re a d y?
N
co m m a n d re g iste r re a d y?
N
Y
Y
w rite p a ra m e te r re g iste rs w rite co m m a n d re g iste r
w rite p a ra m e te r re g iste rs w rite co m m a n d re g iste r
p a ssive w a itin g w ith in te rru p t
a ctive w a itin g (p o llin g ) w ith o u t in te rru p t
sw iti_ 0 3 2 .e m f
Figure 25
Order of Register Access
Preliminary Data Sheet
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PRELIMINARY Programming the Device
6.1
Read and Write Access
For the read and write access it is necessary to distinguish between a connection and configuration command. The connection command register is used to establish a connection (described in Chapter 6.11) and the configuration registers are used to configure the device, i.e. set the clock frequency. If the ISTA1:RDY bit is set the connection command register is ready to receive data from the P interface. If the parameter register and the connection command register are written the RDY bit will be reset from the internal controller. If the connection is established the internal controller will set the RDY bit and the connection command register is ready for the next write or read access. The ISTA1:RDY can be enabled to generate an interrupt to indicate that the device is ready to receive the data, otherwise the P must poll the ISTA1:RDY bit. The configuration command register works independent from the RDY bit. Note: There must be a recovery time period of 120 ns after every configuration command write access to the next write access (command or parameter register).
Preliminary Data Sheet
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PRELIMINARY Programming the Device
6.2
Interrupt Handling
The SWITI interrupt concept consists of four interrupt status register with their corresponding mask register. The five interrupt status register can be divided in one main register, and two error interrupt register, one general purpose interrupt register and one time-slot value register. Every secondary status register and the time-slot value register has a bit in the main register to indicate the set of an interrupt in the assigned error or general purpose register or to indicate a new value in the time-slot value register. The interrupt status register can be read via the microprocessor interface. The NFC and RDY will be set and reset from the internal controller. When an interrupt occurs one or more of the bit GPIO, TSA, ER2, or ER1 is set, then the assigned secondary interrupt status register or time-slot value register must be read first in order to check for the cause of the interrupt. After a secondary status register read access, the error status register and the corresponding bit in the Interrupt Status Register 1 (ISTA1) will be reset.
APLL
STR
ER2
ER 1
G PIO
TSA
N FC
R DY
M ain Status Register Tim e Slot Value Register
Interrupt Error Status R egister 2
Interrupt Error Status R egister 1
G eneral Purpose Interrupt Status R egister
sw iti_ 063 .em f
Figure 26
8-bit P Access Interrupt Structure
The IREQ output is level active. It stays active until all interrupt sources have been serviced. If a new status bit is set while an interrupt is being serviced (P read access), the IREQ pin stays active. For the duration of a write access to the INTM1 register the IREQ line is deactivated. When using an edge-triggered interrupt controller, it is thus recommended to rewrite the INTM1 register at the end of any interrupt service routine. APLL, STR, RDY and NFC Bits If the internal controller does set the RDY bit for the first time and the bit is not masked an interrupt will be generated. If the P reads the ISTA1 register the interrupt will be deactivated. The RDY bit is still active and can be reset from the internal controller. The NFC, STR and APLL bits are not set by any interrupt and therefore can not be masked. Setting these bit does not generate any interrupt. The NFC bit is set from the internal controller if no further connections can be established. The STR bit is set from the internal stream to stream controller if a stream to stream connection is configured. The APLL bit is set from the internal analog PLL controller if the PLL is locked.
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PRELIMINARY Masking Interrupts If an interrupt is not masked (enabled) the IREQ pin will be active if one of the status bits in the interrupt status register is set. The mask bit prevents that the IREQ pin will be active if the status bit is set. The mask bits for the error status registers or general purpose interrupt register disables the interrupt indication for the interrupt status register. Only the interrupt status register can set the IREQ pin if the bit is not masked. Interrupt Structure for a 16-bit Microprocessor Access Programming the Device
APLL STR
ER1
GPIO
TSA
NFC
RDY
Time Slot Value Register
Interrupt Error Status Register 1
switi_068.emf
Figure 27
16-bit P Access Interrupt Structure
In opposite to the 8-bit P access there is only one bit (ER1) to indicate a change in the 16-bit Interrupt Error Status Register 1.
Preliminary Data Sheet
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6.3
Command and Register Overview
The following table (Table 22) shows which parameter registers are considered by issuing an appropriate connection command. Table 22 Command Connect/Disconnect (without subchannels) Connect (with subchannels) Disconnect (with subchannels) Send Message Stop Message Disconnect Part of Broadcast (without subchannels) Disconnect Part of Broadcast (with subchannels) Multipoint Connect/ Disconnect Bidirectional Connection Disconnect All Memory Dump (Connection and Data Memory) x x x x x x x x x x x x x x x x x Affected Registers for Connection Commands Registers SPA ITSA SCA DPA OTSA MV GI1 GI2 CON x x x x x x x x x x x x x x x x x x x
Preliminary Data Sheet
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PRELIMINARY Programming the Device
The following table (Table 23) shows which parameter registers are considered by issuing an appropriate configuration command. Table 23 Command Set H.1x0 Master/ Slave PLL Primary Master Ref. PLL Secondary Master Ref. PLL Source Selection H.100/H.110 Clock Output PCM Clock Output Comp. Clock Output CT_NETREF_1(2 ) Output H.100/H.110 Fallback Set Bit Rate Local Bus Set Bit Rate H.100/H.110 Read Time-Slot Stream to Stream Switch Clock Shift External Input Frequency Set Parallel Mode Set IREQ Pin x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x Affected Registers for Configuration Commands Registers CMD1 CMD2 SPA ITSA SCA DPA OTSA GI1 GI2 TSV
Preliminary Data Sheet
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PRELIMINARY Table 23 Command PCM and H.1x0 Standby Set Loop Frame Signal GPCLK Clock Set Range of Data Rate Read Configuration Read GPCLK Configuration Read PCM Line Configuration Read H.1x0 Line Configuration Read Bit Shift Configuration Software Reset x x x x x x x x x x x x x x x x x x x Programming the Device
Affected Registers for Configuration Commands (cont'd) Registers CMD1 CMD2 SPA ITSA SCA DPA OTSA GI1 GI2 TSV
The command registers have the following structure: 7 I3 6 I2 5 I1 4 I0 3 CC3 2 CC2 1 CC1 0 CC0
CC3..0 is the command code and I3..0 is the parameter code. The following tables (Table 24 to Table 25) show all valid values of command and parameter codes and the related function.
Preliminary Data Sheet
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PRELIMINARY Table 24 Command1) Programming the Device
Connection Command and Parameter Codes Command Parameter Code Code (low nibble) (high nibble) 1H 5H 0H 1H 2H 3H xH xH xH 0H 1H 2H 3H 0H 1H xH 0H 1H 0H 1H minimum delay constant delay disable enable address 8-bit connections address 4-bit connections address 2-bit connections address 1-bit connections OR connection of time-slots AND connection of time-slots Note
Constant Delay Connect Disconnect
address 8-bit connections address 4-bit connections address 2-bit connections address 1-bit connections
Minimum Delay Connect Send Message Stop Message Disconnect Part of Broadcast
2H 3H 4H 6H
Multipoint Connect Disconnect All Bidirectional Connect Memory Dump
1)
7H 8H 9H AH
The input port is determined in SPA Bit4..0 and the output port in DPA Bit4..0. The input time-slot is determined in ITSA and the output time-slot in OTSA.
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PRELIMINARY Table 25 Command Programming the Device
Configuration Command 1 and Parameter Codes Command Parameter Code Code (low nibble) (high nibble) BH 0-3H 4-7H 8-BH C-FH Note
Set Bit Rate Local Bus1)
no effect set bit rate of local input port (2/4/8/ 16 Mbit/s) set bit rate of local output port (2/4/8/16 Mbit/s) set for both input and output (2/4/8/16 Mbit/s) set bit rate of port# to 2 Mbit/s set bit rate of port# to 4 Mbit/s set bit rate of port# to 8 Mbit/s set bit rate for all ports to 8 Mbit/s read time-slot of input port read time-slot of output port Release Connection w. Mode 05) Establish Connection w. Mode 0 Release Connection w. Mode 1 Establish Connection w. Mode 1 Release Connection w. Mode 2 Establish Connection w. Mode 2 Release Connection w. Mode 3 Establish Connection w. Mode 3 Release all programmed stream to stream connections set bit shift of input line set bit shift of all input lines set bit shift of all output lines set bit shift of all input and output lines
Set Bit Rate H.100/H.110 Bus2)
CH
0H 1H 2H 3H 0H 1H 0H 4H 1H 5H 2H 6H 3H 7H 8H-FFH 0H 1H 2H 3H
Read Time-Slot3) Stream-toStream4)
DH EH
Bit Shift6)
FH
1) 2) 3) 4) 5) 6)
the input and output port is determined in SPA, DPA the port is determined in SPA the time-slot is determined in SPA and ITSA or DPA and OTSA source and destination are determined in SPA, DPA see "Stream-to-Stream Connection Mapping" on page 28 the input line is determined in SPA, the shift information in GI1
Preliminary Data Sheet
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PRELIMINARY Table 26
Command
Programming the Device
Configuration Command 2 and Parameter Code
Command Code (low nibble) Parameter Note Code (high nibble)
External Frequency Parallel Mode
1H 2H
0H 1H 0H 1H
set frequency to 32.768 MHz set frequency to 16.384 MHz disable enable = first 8 local input bus lines are parallel and first 8 local output lines are parallel IREQ is active low, timer = 20 ns IREQ is active high, timer = 20 ns IREQ as open-drain, timer = 20 ns IREQ is active low, timer = 300 ns IREQ is active high, timer = 300 ns IREQ as open-drain, timer = 300 ns disable PCM and H-Bus enable PCM and disable H-Bus disable PCM and enable H-Bus enable PCM and H-Bus no loop at all enable PCM and disable H-Bus loop disable PCM and enable H-Bus loop enable PCM and H-Bus loop signal is high active signal is low active XXX is the line address parameter code is line address logical OR connection from min. and max. codes
Set IREQ Pin
3H
0H 1H 2H 4H 5H 6H 0H 1H 2H 3H 0H 1H 2H 3H
PCM - H.1x0 Standby
4H
Loop
5H
Frame Signal1)
6H
0XXXb 1XXXb 0H-7H 0H-6H 8H-AH
GPCLK as Clock2) Range of Data Rate
7H 8H
Preliminary Data Sheet
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PRELIMINARY Table 26
Command
Programming the Device
Configuration Command 2 and Parameter Code (cont'd)
Command Code (low nibble) Parameter Note Code (high nibble)
Read Configuration3)
9H
0H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH
Master/Slave configuration PLL Primary Reference - Master PLL Secondary Ref. - Master PLL Source - Slave Clock Output Selection - H.1x0 Clock Output Selection - PCM Clock Ouput Selection for Interoperability Signals Output Selection - CT_NETREF_1 Output Selection - CT_NETREF_2 H.1x0 Fallback - Phase Alignment External Input Frequency Parallel Mode IREQ Pin H.1x0/PCM Standby Loop Range of Data Rate parameter code is line address Data Rate of Input Line6) Data Rate of Output Line7) Data Rate of H.1x0 Line9) Shift Value for Input Line9) Shift Value for all Output Lines
Read GPCLK Configuration4) Read PCM Line Configuration5) Read H.1x0 Line Configuration8) Read Bit Shift Configuration10)
1) 2) 3) 4) 5) 6) 7) 8) 9) 10)
AH BH CH DH
0H-7H 0H 1H 0H 1H
offset and width are determined in GI1 and GI2 frequency is determined in GI1 The result can be read from the TSV register The result can be read from the TSV and CON register The result can be read from the TSV register SPA must be used for line number DPA must be used for line number The result can be read from the TSV register SPA must be used for line number The result can be read from the TSV register
Preliminary Data Sheet
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6.4
Indirect Configuration Register Access
It is possible to read the current SWITI configuration with an indirect register access for analyze and test purpose. There are five commands in the CMD2 register which can be used to read the configuration. The clock generator output signal and external configuration for the SWITI can be read with the 'Read Configuration Command'. The four instruction bits select one possible configuration command. The current configuration is determined by the command written in the TSV register. The configuration information for every command can be found on page 58. The line configuration can be read with two commands 'Read PCM Line configuration' and 'Read H.1x0 Line configuration'. Before one of these commands will be issued the SPA or DPA register must be written with the port number. The configuration for the selected line is written in the TSV register by the internal controller. The interrupt handling is described in Chapter 6.2. The bit shift configuration can be read with the command 'Read Bit Shift Configuration' and the dataflow is the same as described above. With the command 'Read GPCLK Configuration' it is possible to read the configuration for every GPCLK line. If this command was written the configuration can be read from the TSV and CON register. The CON register is not interrupt controlled and will keep the last data after a microprocessor read access. To read the correct configuration data from the TSV register it is not allowed to use the command "Read Time-Slot Value" before the TSV register was read.
Preliminary Data Sheet
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PRELIMINARY Programming the Device
6.5
Initialization Procedure
After the reset process the PLL, H.1x0 interface, PCM interface, and some other signals need to be initialized. Since the SWITI offers the possibility to use two different external crystal/oscillator frequencies the command 'Set external frequency' must be used first to set the correct frequency and to set the correct value of the input frequency for the APLL. After approximately 750 s the APLL is locked and the APLL status bit is set and the next commands can be written.
R e s e t (H a rd w a re ) In te rn a l F re q u e n c y = e x t. F re q u e n c y
W rite 4 1 H to C M D 2 (if e x t. F re q . = 3 2 .7 6 8 M H z ) W rite 5 1 H to C M D 2 (if e x t. F re q . = 1 6 .3 8 4 M H z )
W A IT ~750s
R e a d In te rru p t S ta tu s R e g is te r 1
N IS T A 1 :A P L L = 1 ? Y A P L L is lo c k e d In t. F re q u e n c y = 4 9 .1 5 2 M H z
s w iti_ 0 7 3 .e m f
Figure 28
Initialization Procedure after Reset
Preliminary Data Sheet
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PRELIMINARY Programming the Device
After this initialization procedure the different functional blocks of the SWITI can be programmed. - - - - - H.1x0 Interface PCM Interface Interrupt's and IREQ Pin GPCLK's and Frame Signals General Purpose Interface
6.6
H.1x0 Clocking Unit
If the HTSI in H-mode is used the the clock generator (PLL) for the H.1x0 interface must be programmed first. This chapter can be skipped for the M-mode. For the PLL synchronization please refer to Chapter 3.4.5 on page 36. They are three program sequences for the H.1x0 interface: - Program the H.1x0 fallback mechanism and PLL inputs for H.1x0 master or slave - Program all output clock signals for the master configuration - Program the frame signals for the slave configuration Program the PLL Source and H.1x0 Clock Fallback The program sequence for the PLL source programming and/or H.1x0 clock fallback must be finished with the command 'H.1x0 Master/Slave Selection' in the CMD1 register. Whenever the PLL source or the H.1x0 clock fallback was changed the H.1x0 Master/ Slave Selection' command must be programmed after this changes Example: A typical H.100 master or slave configuration is shown in Figure 29. Slave Configuration: - CT_C8_A as PLL input reference - Enable clock monitoring (CT_C8_A, CT_C8_B) - Enable automatic clock fallback from CT_C8_A to CT_C8_B H.100 Primary Master Configuration: - - - - NTWK_1 = 8 KHz as primary PLL reference CT_NETREF = 1.544 MHz as fallback PLL reference Enable automatic clock fallback for the primary master Enable automatic switch back to NTWK_1 if NTWK_1 returns
H.100 Secondary Master Configuration - CT_C8_A as primary PLL reference - NTWK_1 = 8 KHz as fallback PLL reference - Enable automatic clock fallback for the secondary master to NTWK_1
Preliminary Data Sheet
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PRELIMINARY Programming the Device
PLL is locked
H.1x0 as Slave Select CT_A as PLL source Write 54H to CMD1
H.100 as Primary Master Select NTWK_1 (8 KHz) as primary PLL source Write 00H to GI1 Write 52H to CMD1
H.100 as Secondary Master Select CT_A clocks as PLL primary source Write 72H to CMD1
Enable automatic clock fallback with clock monitoring Write BAH to CMD1
Select CT_NETREF (1.544 MHz) as secondary PLL source Write 03H to GI1 Write 13H to CMD1
Select NTWK_1 (8 KHz) as PLL secondary source Write 00H to GI1 Write 33H to CMD1
Set the H.1x0 interface as Slave Write 01H to CMD1
Enable automatic fallback mechanism. Enable automatic switch back to prim. source Write 5AH to CMD1
Enable automatic fallback mechanism. for secondary master Write 2AH to CMD1
H.1x0 Slave is configured Set the H.100 interface as Master Write 11H to CMD1
Set the H.100 interface as Master Write 11H to CMD1
H.100 Primary Master is configured
H.100 Secondary Master is configured
switi_074.emf
Figure 29
H.100 Master and Slave Configuration Process
Program the Output Clocks Example: HTSI in H-Mode is configured as H.100 primary master and CT_C8_A with / CT_FRAME_A shall be driven and the MVIP-90 clock signals shall be driven. If H.100 primary master is configured then - Write 15H to CMD1 - Write 17H to CMD1 Example: HTSI in H-Mode is configured as H.100 secondary master and the CT_B clocks shall be driven. If H.100 secondary master is configured then - Write 25H to CMD1
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PRELIMINARY Example: HTSI in H-Mode is configured as H.100 slave and the CT_NETREF_1 signal shall be provided. The signal is inverted and the source signal is NTWK_1. If H.100 slave is configured then - Write 38H to CMD1 Programming the Device
6.7
PCM Clocking Unit
If the HTSI in H-mode is used the H.1x0 clock generator must be programmed first. The PCM clock signals for the line interface will be provided from external PCM devices if the SWITI is used as PCM clock slave or will be provided from the internal PLL if the SWITI is used as PCM clock master. This PCM clock configuration can be programmed with the special command 'PCM Input/Output Selection' in the Figure CMD1 register. For the PLL synchronization please refer to Chapter 3.4.5 on page 36. Example: HTSI in M-Mode as PCM clock master, PLL reference is NTWK_1 with 8 KHz and PDC is driven with 8.192 MHz and PFS is driven. - Write 00H to GI1 - Write 52H to CMD1 - Write B6H to CMD1 Example HTSI in M-Mode as PCM clock slave, PLL reference is PDC with 4.096 MHz. - Write 05H to GI1 - Write 22H to CMD1 - Write 26H to CMD1 (PDC = 4.096 MHz and PFS as input)
6.8 6.8.1
H.1x0/PCM Line Interface Standby Command
All H.1x0 and PCM lines are in a high impedance state after the reset process. If they are configured (data rate, bit shift) they can be enabled with the standby command. During the normal operation the PCM and H.1x0 lines can be enabled or disabled with the standby command. If the lines are disabled the device works internally like an active device.
Preliminary Data Sheet
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PRELIMINARY Example: Set all output PCM lines to high impedance. - Write 24H to CMD1 (I1 must be set to '1' because only PCM shall be tristated) Programming the Device
6.8.2
Determining Clock Rates
The data rate range command is necessary to optimize the minimum delay feature. After the reset process the device assumes a bit rate of 2.048 Mbit/s for all PCM and H.1x0 lines. The command must be issued if other data rates are used. Example (8-bit P interface): 1. Specify that only 2.048 Mbit/s and 4.096 Mbit/s are used for following Set Bit Rate Command. - Write 38H to CMD2 2. Set bit rate of 4.096 Mbit/s on local bus input line 8 and local bus output line 1 - Write 08H to SPA - Write 01H to DPA - Write DBH to CMD1 3. Set bit rate of 2.048 Mbit/s on H-bus line 8 - Write 88H to SPA - Write 0CH to CMD1 Example (16-bit P interface): 1. - Write 38H to CMD2 2. - Write 0008H to SA - Write 0001H to DA - Write DBH to CMD1 3. - Write 0008H to SA - Write 0CH to CMD1
Preliminary Data Sheet
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6.8.3
Performing Bit Shifting
The bit shift is performed on half-bit steps, not on a clock basis. It is a true bit shift, it means that with a data rate equals to the data clock frequency (e.g. 4.096 Mbit/s with 4.096 MHz data clock) programming a bit shift of 1-bit results on a shift of 1 clock period, and programming a shift of half-bit the result is a shift of half clock period. Running in double data clock rate (e.g. 4.096 Mbit/s with 8.192 MHz data clock), a bit shift of 1-bit results on a shift of 2 clock periods and a shift of half-bit will result on a shift of 1 clock period.
6.8.3.1
Input Bit Shifting
PFS
0 1 2 3 4 7 0
D ata R ate o f the S electe d L ine Lo cal bus Inp ut Line 8 TS 0
sw iti_0 40.em f
Figure 30
Example: Input Bit Shifting
Example (8-bit P interface): Begin time-slot 0 of local input line 8 with the 4th rising edge relative to one byte before the PFS rising edge. The bits are internally sampled with the falling edge. - Write 08H to SPA - Write 08H to GI1 - Write 0FH to CMD1 Example (16-bit P interface): - Write 0008H to SA - Write 0008H to GI - Write 0FH to CMD1
Preliminary Data Sheet
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PRELIMINARY Programming the Device
6.8.3.2
Output Bit Shifting
PFS
0 1 2 7
D a ta R ate of th e Lin e L ocal bu s O utpu t Lin e s
TS 0
sw iti_04 1.em f
Figure 31
Example: Output Bit Shifting
Example (8-bit P interface): Output time-slot 0 of all output lines begins with the first falling edge relative to the first byte after PFS rising edge. The bits are internally sampled with the rising edge. - Write 01H to GI1 - Write 2FH to CMD1 Example (16-bit P interface): - Write 0001H to GI - Write 2FH to CMD1
Preliminary Data Sheet
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6.9 6.9.1
Global Clock Signals Framing Groups
125s
PFS 16.384 Mbit/s
0 0 1 1 4 244ns 64 125s 4
GPCLK_1
125s 427ns
GPCLK_2
switi_077.emf
Figure 32
Example Framing Groups
Example (8-bit P interface): Frame signal on GPCLK_1 starts with the rising edge of 64th clock cycle and the length is set to 244 ns (4 x 61 ns). - Write 00H to GI1 - Write 61H to GI2 - Write 16H to CMD2
Preliminary Data Sheet
114
2001-11-16
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PRELIMINARY Programming the Device
Frame signal on GPCLK_2 starts with the falling edge of the 4th clock cycle and the length is set to 427 ns (7 x 61 ns). - Write 12H to GI1 - Write C0H to GI2 - Write 26H to CMD2 Example (16-bit P interface): - Write 6100H to GI2 - Write 0016H to CMD2 - Write C012H to GI2 - Write 0026H to CMD2
6.10
Read Time-Slot Value
By issuing this command the time-slot value appears in the register TSV after arriving and an interrupt will be caused and a new read time-slot value will be accepted. The command has to be issued for every read request. The current TSV data will be overwritten if the read time-slot command is issued. Example (8-bit P interface): Read time-slot 10 of local bus input line 3 - Write 03H to SPA - Write 0AH to ITSA - Write 0DH to CMD1 Example (16-bit P interface): - Write 0A03H to SA - Write 0DH to CMD1 Wrong Time-Slot and Time-Out In some case it could be happen that the P tries to read a wrong time-slot. A wrong timeslot is defined as a invalid time-slot number for the selected data rate, i.e. data rate = 2 MBit/s and selected time-slot is 58. If the P tries to read a wrong time-slot no interrupt would be generated and the controller doesn't accept any further commands. The SWITI has a integrated time-out counter to allow a new read time-slot command after the maximum of three frames.
Preliminary Data Sheet
115
2001-11-16
PEF 20451 / 20471 / 24471
PRELIMINARY Programming the Device
6.11
Establish Connections
The following chapter describes the programming of several kinds of connections. The programming interface allows to program or re-program a connection during the normal switching mode. Before a new connection for a specific output time-slot and line will be programmed the specific connection has to be released.
6.11.1
Establish 8-bit Connections
F ra m e S ig n a l L o ca l b u s In p u t L in e 3
TS 10 co n sta n t d e la y
H -B u s I/O L in e 2 2
TS 30
sw iti_ 0 2 7 .e m f
Figure 33
Example: 8-bit Connection
Example (8-bit P interface): Connect time-slot 10 of local bus line 3 with output time-slot 30 of H-Bus line 22 as a constant delay connection - - - - - Write 0AH to ITSA Write 03H to SPA Write 1EH to OTSA Write 96H to DPA Write 01H to CCMD
Example (16-bit P interface): - Write 0A03H to SA - Write 1E96H to DA - Write 0001H to CC16
Preliminary Data Sheet
116
2001-11-16
PEF 20451 / 20471 / 24471
PRELIMINARY Programming the Device
6.11.2
Subchannel Switching
With the subchannel address register (SCA) and the constant delay command it is possible to program 1,2, and 4 connections. The following figure explains the relation between the subchannel address and the corresponding bits in one time-slot.
ISCA from SCA Register 0H 1 OSCA from SCA Register 0 1H
TS IN 0 1
TS OUT
1H
3
2
1
0
3
2
1
0
3H
1H
3
2
1
0
3
2
1
0
2H
6H
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
3H
switi_070.emf
Figure 34
Subchannel Address in Time-Slot
6.11.2.1 Establish 4-bit Connections
F ra m e S ig n a l L o ca l b u s In p u t L in e 3
TS 10
co n sta n t d e la y
H -B u s I/O L in e 2 2
TS 30
sw iti_ 0 2 8 .e m f
Figure 35
Example: 4-bit Connection
Preliminary Data Sheet
117
2001-11-16
PEF 20451 / 20471 / 24471
PRELIMINARY Example (8-bit P interface): Connect low nibble of time-slot 10 of local bus line 3 with high nibble of output time-slot 30 of H-Bus line 22 as a constant delay connection - - - - - - Write 08H to SCA Write 0AH to ITSA Write 03H to SPA Write 1EH to OTSA Write 96H to DPA Write 11H to CCMD Programming the Device
Example (16-bit P interface): - Write 0A03H to SA - Write 1E96H to DA - Write 0811H to CC16
6.11.2.2 Establish 2-bit Connections
F ra m e S ig n a l L o ca l b u s In p u t L in e 3
TS 10
co n sta n t d e la y
H -B u s I/O L in e 2 2
TS 30
sw iti_ 0 4 2 .e m f
Figure 36
Example: 2-bit Connection
Example (8-bit P interface): Connect 2nd 2-bit subchannel of time-slot 10 of local bus line 3 with 4th 2-bit subchannel of output time-slot 30 of H-Bus line 22 as a constant delay connection - - - - - - Write 19H to SCA Write 0AH to ITSA Write 03H to SPA Write 1EH to OTSA Write 96H to DPA Write 21H to CCMD
118 2001-11-16
Preliminary Data Sheet
PEF 20451 / 20471 / 24471
PRELIMINARY Example (16-bit P interface): - Write 0A03H to SA - Write 1E96H to DA - Write 1921H to CC16 Programming the Device
6.11.2.3 Establish 1-bit Connections
F ra m e S ign a l
L oca l b u s In pu t L in e 3
T S 10
co n sta n t d e la y
H -B u s I/O L in e 2 2
TS 30
sw iti_ 04 3 .e m f
Figure 37
Example: 1-bit Connection
Example (8-bit P interface): Connect 3rd 1-bit subchannel of time-slot 10 of local bus line 3 with 6th 1-bit subchannel of output time-slot 30 of H-Bus line 22 as a constant delay connection - - - - - - Write 2AH to SCA Write 0AH to ITSA Write 03H to SPA Write 1EH to OTSA Write 96H to DPA Write 31H to CCMD
Example (16-bit P interface): - Write 0A03H to SA - Write 1E96H to DA - Write 2A31H to CC16
Preliminary Data Sheet
119
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PEF 20451 / 20471 / 24471
PRELIMINARY Programming the Device
6.11.3
Establish Broadcast Connections
F ra m e S ig n a l
L o ca l b u s In p u t L in e 3
TS 10 co n sta n t d e la y
H -B u s I/O L in e 2 2 H -B u s I/O L in e 2 9
TS 30
TS 98
sw iti_0 31.em f
Figure 38
Example: Broadcast Connection
Example (8-bit P interface): Connect time-slot 10 of local bus line 3 with output time-slot 30 of H-Bus line 22 and output time-slot 98 of H-Bus line 29 in constant delay mode. If the connections are established consecutively it is not necessary to rewrite the source determining registers ITSA and SPA because they keep their values. - - - - - - - - Write 0AH to ITSA Write 03H to SPA Write 1EH to OTSA Write 96H to DPA Write 01H to CCMD Write 62H to OTSA Write 9DH to DPA Write 01H to CCMD
Example (16-bit P interface): - - - - - Write 0A03H to SA Write 1E96H to DA Write 0001H to CC16 Write 629DH to DA Write 0001H to CC16
Preliminary Data Sheet
120
2001-11-16
PEF 20451 / 20471 / 24471
PRELIMINARY Programming the Device
6.11.4
Establish Subchannel Broadcast Connection
F ra m e S ig n a l
Local bus In p u t L in e 3
TS 10
c o n s ta n t d e la y
1
2
3
4
5
Local bus O u tp u t L in e 0
TS 30
s w iti_ 0 8 4 .e m f
Figure 39
Example: Subchannel Broadcast Connection
- First Connection - Write 03H to SCA - Write 0AH to ITSA - Write 03H to SPA - Write 1EH to OTSA - Write 00H to DPA - Write 21H to CCMD - Second Connection - Write 1AH to SCA - Write 0AH to ITSA - Write 03H to SPA - Write 1EH to OTSA - Write 00H to DPA - Write 21H to CCMD - Third Connection - Write 23H to SCA - Write 0AH to ITSA - Write 03H to SPA - Write 1EH to OTSA - Write 00H to DPA - Write 31H to CCMD - Fourth Connection - Write 2AH to SCA - Write 0AH to ITSA - Write 03H to SPA
Preliminary Data Sheet 121 2001-11-16
PEF 20451 / 20471 / 24471
PRELIMINARY - Write 1EH to OTSA - Write 00H to DPA - Write 31H to CCMD - Fifth Connection - Write 08H to SCA - Write 0AH to ITSA - Write 03H to SPA - Write 1EH to OTSA - Write 00H to DPA - Write 21H to CCMD Programming the Device
6.11.5
F ra m e S ig n al
Establish Multipoint Connection
L ocal bu s In pu t L in e 3 L ocal bu s In pu t L in e 8
TS 10
TS 20 co nsta nt de la y OR T S 30
sw iti_0 34 .em f
H -B u s I/O Line 22
Figure 40
Example: Multipoint Connection
Example (8-bit P interface): Connect time-slot 10 of local bus line 3 and time-slot 20 of local bus line 8 logical OR with output time-slot 30 of H-Bus line 22 in constant delay mode. If the connections are established consecutively it is not necessary to rewrite the destination determining registers OTSA and DPA because they keep their values. - - - - - - - - Write 0AH to ITSA Write 03H to SPA Write 1EH to OTSA Write 96H to DPA Write 07H to CCMD Write 14H to ITSA Write 08H to SPA Write 07H to CCMD
Preliminary Data Sheet
122
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PEF 20451 / 20471 / 24471
PRELIMINARY Example (16-bit P interface): - - - - - Write 0A03H to SA Write 1E96H to DA Write 0007H to CC16 Write 1408H to SA Write 0007H to CC16 Programming the Device
6.12
Send Messages
Sending messages means to transmit a constant value on any time-slot or subchannel after the message is programmed within three frames. That means a message has always a minimum delay and is sent until the sending is stopped by the stop message command.
F ra m e S ig n a l L o ca l b u s O u tp u t L in e 3
TS 10
FFH
sw iti_ 0 2 9 .e m f
Figure 41
Example: Send Message
Example (8-bit P interface): Send constant value of FFH on time-slot 10 of local bus line 3 - - - - Write FFH to MV Write 0AH to OTSA Write 03H to DPA Write 03H to CCMD
Example (16-bit P interface): - Write FFH to MV - Write 0A03H to DA - Write 0003H to CC16
Preliminary Data Sheet
123
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PEF 20451 / 20471 / 24471
PRELIMINARY Programming the Device
6.13 6.13.1
Release Connections Release 8-bit Connections
Example (8-bit P interface): Release connection established in Figure 33 - - - - - Write 0AH to ITSA Write 03H to SPA Write 1EH to OTSA Write 96H to DPA Write 05H to CCMD
Example (16-bit P interface): - Write 0A03H to SA - Write 1E96H to DA - Write 0005H to CC16
6.13.2
Release 4-bit Connections
Example (8-bit P interface): Release connection established in Figure 35 - - - - - - Write 08H to SCA Write 0AH to ITSA Write 03H to SPA Write 1EH to OTSA Write 96H to DPA Write 15H to CCMD
Example (16-bit P interface): - Write 0A03H to SA - Write 1E96H to DA - Write 0815H to CC16
6.13.3
Release 2-bit Connections
Example (8-bit P interface): Release connection established in Figure 36 - Write 19H to SCA - Write 0AH to ITSA - Write 03H to SPA
Preliminary Data Sheet 124 2001-11-16
PEF 20451 / 20471 / 24471
PRELIMINARY - Write 1EH to OTSA - Write 96H to DPA - Write 25H to CCMD Example (16-bit P interface): - Write 0A03H to SA - Write 1E96H to DA - Write 1925H to CC16 Programming the Device
6.13.4
Release 1-bit Connections
Example (8-bit P interface): Release connection established in Figure 37 - - - - - - Write 2AH to SCA Write 0AH to ITSA Write 03H to SPA Write 1EH to OTSA Write 96H to DPA Write 35H to CCMD
Example (16-bit P interface): - Write 0A03H to SA - Write 1E96H to DA - Write 2A35H to CC16
Preliminary Data Sheet
125
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PRELIMINARY Programming the Device
6.13.5
Release Broadcast Connection
Example (8-bit P interface): Release connection established in Figure 38. All but the last connection participating on a broadcast connection have to be released by the Disconnect Part of Broadcast Command. The last connection has to be released by the Constant Delay Connect Disconnect Command. - - - - - - - - - - Write 0AH to ITSA Write 03H to SPA Write 62H to OTSA Write 9DH to DPA Write 06H to CCMD Write 0AH to ITSA Write 03H to SPA Write 1EH to OTSA Write 96H to DPA Write 05H to CCMD
Example (16-bit P interface): - - - - - - Write 0A03H to SA Write 629DH to DA Write 0006H to CC16 Write 0A03H to SA Write 1E96H to DA Write 0005H to CC16
6.13.6
Release Subchannel Broadcast Connection
The order can be different as the establish order. The last release must be a normal release command. - First Connection - Write 03H to SCA - Write 0AH to ITSA - Write 03H to SPA - Write 1EH to OTSA - Write 00H to DPA - Write 26H to CCMD - Second Connection - Write 1AH to SCA - Write 0AH to ITSA - Write 03H to SPA - Write 1EH to OTSA
Preliminary Data Sheet 126 2001-11-16
PEF 20451 / 20471 / 24471
PRELIMINARY - Write 00H to DPA - Write 26H to CCMD - Third Connection - Write 23H to SCA - Write 0AH to ITSA - Write 03H to SPA - Write 1EH to OTSA - Write 00H to DPA - Write 36H to CCMD - Fourth Connection - Write 2AH to SCA - Write 0AH to ITSA - Write 03H to SPA - Write 1EH to OTSA - Write 00H to DPA - Write 36H to CCMD - Fifth Connection - Write 08H to SCA - Write 0AH to ITSA - Write 03H to SPA - Write 1EH to OTSA - Write 00H to DPA - Write 25H to CCMD Programming the Device
6.13.7
Release Multipoint Connection
This type of connections is released with normal disconnect commands. (See "Release 8-bit Connections" on page 124.)
6.14
Stop Sending Messages
Example (8-bit P interface): Stop sending message invoked in Figure 41 - Write 0AH to OTSA - Write 03H to DPA - Write 04H to CCMD Example (16-bit P interface): - Write 0A03H to DA - Write 0004H to CC16
Preliminary Data Sheet
127
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PEF 20451 / 20471 / 24471
PRELIMINARY Timing Diagrams
7
7.1
Timing Diagrams
PCM Interface Timing
The following tables and figures give the PCM timing with a capacitive load of 50 pF. PDC and PFS are configured as inputs. The timing is also valid if PDC and PFS are configured as outputs.The PFS output high time is fixed to 488 ns for all data rates and clock rates.The PFS input minimum high time depends on the PDC input frequency (see table Table 27)
tPFS
tFS
PFS tsFS thFS tf tCLK_H
tr PDC
tCLK_L tsIN IN Bit 7
thIN
Bit 6
tdOUT
OUT TS63 4Mbit/s
Bit 7
Bit 6
switi_057.emf
TS0
Figure 42
PCM Timing
Preliminary Data Sheet
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PRELIMINARY Table 27 Parameter Period PFS PFS high time PFS set up time to clock PFS hold time from clock PFS high time PFS set up time to clock PFS hold time from clock PFS high time PFS set up time to clock PFS hold time from clock PFS high time PFS set up time to clock PFS hold time from clock PDC clock period PDC clock period low PDC clock period high PDC clock period PDC clock period low PDC clock period high PDC clock period PDC clock period low PDC clock period high PDC clock period PDC clock period low PDC clock period high PDC rise time PDC fall time PCM Timing Symbol tPFS tFS tsFS thFS tFS tsFS thFS tFS tsFS thFS tFS tsFS thFS tCLK tCLK_L tCLK_H tCLK tCLK_L tCLK_H tCLK tCLK_L tCLK_H tCLK tCLK_L tCLK_H tr tf 480 15 20 240 15 20 120 10 20 60 10 20 480 232 233 240 112 113 120 51 52 60 26 27 34 35 10 10 70 71 131 132 251 252 Limit Values min. max. 125 s ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns PDC = 16.384 MHz PDC = 8.192 MHz PDC = 4.096 MHz PDC = 2.048 MHz PDC = 16.384 MHz PDC = 8.192 MHz PDC = 4.096 MHz PDC = 2.048 MHz Unit Test Condition Timing Diagrams
Preliminary Data Sheet
129
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PRELIMINARY Table 27 Parameter Serial data input set up time Serial data input set up time Serial data input set up time Serial data input set up time Serial data output delay Serial data output delay Serial data output delay Serial data output delay
1)
Timing Diagrams
PCM Timing (cont'd) Symbol tsIN 20 30 20 30 20 30 20 30 0 0 0 0 30 30 30
1) 1) 1)
Limit Values min. max.
Unit ns
Test Condition
PDC = 2.048 MHz ns ns PDC = 4.096 MHz ns ns PDC = 8.192 MHz ns ns PDC = 16.384 MHz ns ns ns ns ns PDC = 2.048 MHz PDC = 4.096 MHz PDC = 8.192 MHz PDC = 16.384 MHz tdOUT tdOUT tdOUT tdOUT tsIN tsIN tsIN
Serial data input hold time thIN
Serial data input hold time thIN
Serial data input hold time thIN
Serial data input hold time thIN
30 1)
for PCM master, the maximum delay is 15 ns
Preliminary Data Sheet
130
2001-11-16
PEF 20451 / 20471 / 24471
PRELIMINARY Timing Diagrams
7.2
PCM Parallel Mode Timing
TIME SLOT PDC
255
0
1
TCLK_L
2
3
TCLK_H TFS TFH TCLK
PFS
TDS TDH
TS3 VALID DATA
IN
TDD
TS1 VALID DATA
OUT
switi_071.emf
Figure 43 Table 28 Parameter
Parallel Mode Timing PCM Parallel Mode Timing Symbol TFS TFH TDS TDH TDD TCLK TCLK_H TCLK_L 483 231 231 Limit Values min. max. ns ns ns ns 35 493 257 257 ns ns ns ns PDC = 2.048 MHz 125 125 50 15 Unit Test Condition
Frame setup time to clock Frame hold time to clock Input data setup time Input data hold time Output data delay PDC clock period PDC clock period high PDC clock period low
Preliminary Data Sheet
131
2001-11-16
PEF 20451 / 20471 / 24471
PRELIMINARY Timing Diagrams
7.3
H-Bus and PCM (Local Bus) Frame Structure
Figure 44 shows the H-Bus clock alignment together with the PCM (local bus) clock alignment.
F ra m e B o u n d a ry
PFS
PDC@ 2 M Hz
PDC@ 4 M Hz
PDC@ 8 M Hz
PDC@ 16 M Hz
C T _ F R A M E (A /B )
C T _ C 8 (A /B )
FR_CO M P
C16
C2
C4 SCLK (2 .0 4 8 M H z ) SC LKx2* (2 .0 4 8 M H z ) SCLK (4 .0 9 6 M H z ) SC LKx2* (4 .0 9 6 M H z ) SCLK (8 .1 9 2 M H z ) SC LKx2* S C L K -D (8 .1 9 2 M H z )
s w iti_ 0 7 9 .e m f
Figure 44
H-Bus and PCM (Local Bus) Clock Alignment
132 2001-11-16
Preliminary Data Sheet
PEF 20451 / 20471 / 24471
PRELIMINARY
125 s C T_FRAM E CT_C8 CT_Dx T im e S lo t 8 1 2 3 4 0 5 6 7 8 1 2 3 4 5 6 7 8 1
Timing Diagrams
127
sw iti_ 0 0 6 .e m f
Figure 45
H-Bus Frame Structure
CT_FRAM E CT_C8 D a ta O u t D a ta In 1 Bit Cell
sw iti_012.em f
Bit 8
Bit 1
Figure 46
H.1x0 Detailed Functional Timing
125 s
CT_FR AM E CT_C8 T im e -S lo t 0 C T_D x 8 M b it/s C T_Dx 4 M b it/s C T_Dx 2 M b it/s 8 1 2 3 4 5 6 7 8 1 2 3 T im e -S lo t 1 2 7 4 5 6 7 8 1
T im e -S lo t 6 3 1 1 2 3 4 5 6 7 8 8
T im e -S lo t 3 1 1 1 2 7 8 8
sw iti_ 0 6 4 .e
Figure 47
H.1x0 Functional Timing for 8, 4 and 2 MBit/s Data Streams
Preliminary Data Sheet
133
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PRELIMINARY Timing Diagrams
Note: The MSB (PCM sign bit) must be at the beginning (first bit) of the time-slot for PCM data. For other data types (e.g. HDLC) the MSB may be first or last depending on the format. The SWITI doesn't convert the data format between the PCM and H.1x0 interface.
7.4
H-Bus Timing
1 -B it C ell T fs T fh 2 .0V 0 .6V T fp T c8h C T _C 8 0 .6V T c8 p T zdo D a ta O ut T s 12 7 B it 8 T do z T dv D ata In T div T sam p 1 .4V T s 0 B it 1 0 .4V 0.8V T do d H .1 00 2 .4V H .1 10 2.0V T c8 l 2 .0V
C T _F R A M E
sw iti_ 00 7 .e m f
Figure 48
Detailed Data Bus Timing
Measuring conditions, data lines - - - - Vth (threshold voltage) = 1.4 V Vhi (test high voltage) = 2.0 V Vlo (test low voltage) = 0.8 V Input signal edge rate = 1 V/ns
Measuring conditions, clock and frame lines - Vt+ (test high voltage) = 2.0 V - Vt- (test low voltage) = 0.6 V - Input signal edge rate = 1 V/ns
Preliminary Data Sheet
134
2001-11-16
PEF 20451 / 20471 / 24471
PRELIMINARY Table 29 Symbol Component Timing Specification Parameter Clock edge rate (All Clocks except CT_NETREF) CT_NETREF edge rate Tc8p Tc8h Tc8l Tsamp Tdoz Tzdo Tdod Tdv Tdiv Tfp Tfs Tfh Clock CT_C8 Period Clock CT_C8 High Time Clock CT_C8 Low Time Data Sample Point Data Output to HiZ Time Data HiZ to Output Time Data Output Delay Time Data Valid Time Data Invalid Time CT_FRAME Width CT_FRAME Setup Time CT_FRAME Hold Time Phase Correction - 10 0 0 0 102 90 45 45 0 122 122.066- 49- 49- 90 0 23 23 83 112 180 90 90 10 Min 0.25 Typ Max 2 Unit V/ns Notes 1 Timing Diagrams
0.3 122.074+ 73+ 73+
V/ns ns ns ns ns ns ns ns ns ns ns ns ns ns
16 5 6, 12 6, 12 9 3, 7, 10 3, 7, 10 3, 7 8, 15,17 13, 14
Note:
11
1. The rise and fall times are determined by the edge rate in V/ns. A "Max" edge rate is the fastest rate at which a clock transitions. 2. Test Load: 200 pF 3. Test Load: 70 pF 4. When RESET is active, every output driver is tristated. 5. Tc8p Min and Max are under free-run conditions assuming 32ppm clock accuracy. 6. Non-cumulative, Tc8p requirements still need to be met. 7. Measured at the transmitter. 8. Measured at the receiver. 9. For reference only. 10.Tdoz and Tzdo apply at every time-slot boundary. 11. (Phase Correction) results from PLL timing corrections. 12.Duty Cycle measured at transmitter under no load conditions. 13.This range accounts for (Phase Correction) 14.H.110: Tcell = Max. clock backplane delay + Max. data backplane delay + Max. Tzdo + (Min. Tdiv - Max. Tdv) + Max. Tdoz + = 26 ns + 46 ns + 11 ns + (102 ns - 83 ns) + 10 ns + 10 ns = 122 ns. Max. clock delay and max. data delay are worst case numbers based on electrical simulation. 15.Based on worst case electrical simulation. 16.H.110: 10%-90%. Test Load = 150 pF. 17.Tdv = Max. clock backplane delay + Max. data backplane delay + Max. data HiZ to output time = 26 ns + 46 ns + 11 ns = 83 ns. Max. clock delay and max. data delay are worst case numbers based on electrical simulation.
Preliminary Data Sheet
135
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PRELIMINARY Timing Diagrams
Vt+
Vt+
CT_C8_A
CT_C8_A
Tskc8 Vt+
Tskcomp Vt+
CT_C8_B
inter-operability and PCM (local bus) clocks
switi_080.emf
Figure 49 Table 30 Symbol Tskc8
Clock Skew Timing Clock Skew Timing Parameter Max Skew between CT_C8 "A" and "B" Min Max 16 17 5 1.2 0.6 0.4 10 2 1.6 Unit Notes ns ns ns V V V pF 5 5 5 5 1,2,3,4 1
Tskcomp Max Skew between CT_C8_A and any generated compatibility clock Tskout Vt+ VtVhys Cin Note: Max Skew between all SWITI output clocks Positive-going Threshold Negative-going Threshold Hysteresis (Vt+, Vt-) Input pin capacitance
1. Test Load: 50 pF 2. Assumes "A" and "B" masters in adjacent slots. 3. When static skew is 10 ns and, in the same clock cycle, each clock performs a 10 ns phase correction in opposite directions, a maximum skew of 30 ns will occur during that clock cycle. 4. Meeting the skew requirements in Table 30 and the clock accuracy requirements could require the PLLs generating CT_C8 to have different time constants when acting as primary and secondary clock masters. 5. Requirements for CT_C8 and CT_FRAME receivers.
Preliminary Data Sheet
136
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PRELIMINARY Timing Diagrams
7.5
Clock Interoperability
CT_C8
Tcrs
SCLK-D
Tsh Tsl
switi_066.emf
Figure 50 Table 31
SCLK-D Timing for SCbus Operating at 8.192 Mbit/s SCLK-D Timing at 8.192 Mbit/s
Symbols Parameter Tcrs Tsh Tsl
Note:
Min. 100 51 51
Typ.
Max. 110
Unit ns ns ns
Rising Edge of CT_C8_n to Rising Edge of SCLK-D SCLK-D High Time SCLK-D Low Time
61 61
71 71
1. Rising edge of Ct_C8_n to rising edge of SCLK-D includes 5 ns of skew as with other compatibility signals (n = current primary CT Bus clock signal identifier) 2. SCLK-D high and low times include nominal 3. This timing is valid under conditions specified in the PCI Local Bus Specification, rev. 2.1, Table 4-2, note 4 4. CT_C8 is configured as output and SCLK-D is configured as output.
Preliminary Data Sheet
137
2001-11-16
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PRELIMINARY Timing Diagrams
7.6
Microprocessor Interface Timing
Microprocessor accesses of the SWITI are performed by an activation of the address and CS. - By driving the MODE16 pin 'low' the user selects the 8-bit microprocessor interface, by driving it 'high' - the 16-bit microprocessor interface. - By driving the ALE pin 'high' the user selects Intel/Infineon mode, by driving it 'low' Motorola mode. The pin is sampled during the hardware reset process. - In Intel/Infineon mode, a distinction is needed between working in multiplexed address/data bus mode and de-multiplexed address and data bus mode. In Motorola mode, only de-multiplexed busses are used. By driving the ALE pin 'high' during the normal operation the user selects the de-multiplexed mode, a falling or rising edge during the normal operation selects the multiplexed mode.
7.6.1
Infineon/Intel Timing in De-Multiplexed Mode
In this mode driving RD 'low' causes a read access, driving WR 'low' causes a write access. In de-multiplexed bus configuration, ALE must be driven `high'. Table 32 Parameter Infineon/Intel Timing in De-Multiplexed Mode Symbol Limit Values (CLOAD= 50pF) min Address setup time to WR or RD RD pulse width RD recovery time Data output delay from RD active Data float delay from RD inactive WR pulse width WR recovery time Data setup time to WR x CS Data hold time from WR x CS tAS tRR tRI tRD tDF tWW tWI tDW tWD 40 ns 120 ns 20 ns 10 ns 15 ns 60 ns 120 ns 60 ns 15 ns max
Note: The read/write recovery time (tRI and tWI) are required only for consecutive accesses to the microprocessor interface.
Preliminary Data Sheet
138
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PRELIMINARY Timing Diagrams
tAS A0-A4 Address tRR RDxCS tRD D0-D7 Data tDF tRI
Figure 51
Infineon/Intel Read Cycle in De-Multiplexed Mode
tAS A0-A4 Address tWW tWD tDW WRxCS D0-D7 Data tWI
Figure 52
Infineon/Intel Write Cycle in De-Multiplexed Mode
Addresses will be latched with the falling WR edge during the write cycle internally.
7.6.2
Infineon/Intel Timing in Multiplexed Mode
In this mode the ALE pin is used to lock the address send via the multiplexed A/D bus.
Preliminary Data Sheet
139
2001-11-16
PEF 20451 / 20471 / 24471
PRELIMINARY Table 33 Parameter Infineon/Intel Timing in Multiplexed Mode Symbol Limit Values (CLOAD= 50pF) min ALE pulse width Address setup time to ALE falling edge Address hold time from ALE falling edge Address latch setup time to WR, RD RD pulse width RD recovery time Data output delay from RD active Data float delay from RD inactive WR pulse width WR recovery time Data setup time to WR x CS Data hold time from WR x CS tAA tAL tLA tALS tRR tRI tRD tDF tWW tWI tDW tWD 40 ns 120 ns 20 ns 10 ns 15 ns 15 ns 5 ns 5 ns 60 ns 120 ns 60 ns 15 ns max Timing Diagrams
tAA ALE
tALS
tRR RDxCS tLA AD0-AD7 tAL Address tRD Data tDF
tRI
Address
Figure 53
Infineon/Intel Read Cycle in Multiplexed Mode
Preliminary Data Sheet
140
2001-11-16
PEF 20451 / 20471 / 24471
PRELIMINARY Timing Diagrams
tAA ALE
tALS
tWW WRxCS tLA AD0-AD7 tAL Address tDW Data tWD
tWI
Address
Figure 54
Infineon/Intel Write Cycle in Multiplexed Mode
Preliminary Data Sheet
141
2001-11-16
PEF 20451 / 20471 / 24471
PRELIMINARY Timing Diagrams
7.6.3
Motorola Microprocessor Timing
In this mode R/W distinguishes between Read and Write interactions, and DS is used for timing. DS X CS is active (low) when both, DS and CS, are active (low). The ALE pin must be driven 'low'. Table 34 Parameter Motorola Timing Symbol Limit Values (CLOAD= 50pF) min Address setup time to CSxDS R or W setup to DS R/W hold from CSxDS inactive R pulse width R recovery time Data output delay from R Data float delay from R W pulse width W recovery time Data setup time to W and CS, DS and CS Data hold time from W and CS, DS and CS tAS tDSD tRWD tRR tRI tRD tDF tWW tWI tDW tWD 40 ns 120 ns 10 ns 10 ns 15 ns 0 0 60 ns 120 ns 60 ns 15 ns max
Note: DS X CS is active (low) when, both, DS and CS are active (low)
Preliminary Data Sheet
142
2001-11-16
PEF 20451 / 20471 / 24471
PRELIMINARY Timing Diagrams
tAS A0-A4 Address tDSD R/W tRR CSxDS tRD D0-D7 Data tDF tRI tRWD
Figure 55
Motorola Read Cycle
tAS A0-A4 Address tDSD R/W tWW CSxDS tWD D0-D7 tDW Data tWI tRWD
Figure 56
Motorola Write Cycle
Preliminary Data Sheet
143
2001-11-16
PEF 20451 / 20471 / 24471
PRELIMINARY Timing Diagrams
7.7
Table 35 Parameter
JTAG Interface Timing
JTAG Interface Timing Symbol tTCJ tCJL tCJH tSUJ tHJR Limit Values min. typ. max. ns ns ns ns ns ns ns ns ns 20 25 1 ns ns s In Update-DR TAP Controller State 100 40 40 5 5 5 5 10 10 Unit Notes
Test Clock (TCK) Period Test Clock (TCK) Period Low Test Clock (TCK) Period High TMS Set-up time before TCK Rising Edge TMS Hold time after TCK Rising Edge
TDI Set-up time before TCK tDSE Rising Edge TDI Hold time after TCK Rising Edge Input Data Set-up time Input Data Hold time TDO Delay after TCK Falling Edge Any output pin Delay after TCK Falling Edge Test Reset tDHE tIPJ tIAJ tODF tOPD tTRST
Preliminary Data Sheet
144
2001-11-16
PEF 20451 / 20471 / 24471
PRELIMINARY Timing Diagrams
tTCJ tCJH tCJL
TCK
tSUJ tHJR
TMS
tDSE tDHE
TDI
tODF
TD0
tIPJ tIAJ
any input
tOPD
any output TRST
tTRST
Figure 57
Boundary Scan Timing
Preliminary Data Sheet
145
2001-11-16
PEF 20451 / 20471 / 24471
PRELIMINARY Timing Diagrams
7.8
Table 36 Parameter
Hardware Reset Timing
Hardware Reset Timing Symbol tRESET 1 Limit Values min. typ. max. s Unit Notes
Hardware Reset time
tR E S E T RESET
sw iti_ 0 9 0 .e m f
Figure 58
Hardware Reset Timing
Note: In H.110 mode Table 36 and Figure 58 are also valid for the CT_RESET signal.
Preliminary Data Sheet
146
2001-11-16
PEF 20451 / 20471 / 24471
PRELIMINARY Electrical Characteristics
8
8.1
Table 37 Parameter
Electrical Characteristics
Absolute Maximum Ratings
Absolute Maximum Ratings Symbol Limit Values - 40 to 85 - 65 to 150 - 0.5 to 4.6 - 0.5 to 7 Unit
Ambient temperature under bias PEF Storage temperature Supply voltage I/O Supply voltage Voltage on any input or output pin (referenced to ground) ESD robustness1) (HBM: 1.5 k, 100 pF)
1)
TA Tstg VDD VDD5 VS
C C
V V
- 0.5 to VDD + 0.5 V - 0.5 to VDD5 + 0.5 V
VESD,HBM 1500
According to MIL-Std 883D, method 3015.7 and ESD Ass. Standard EOS/ESD-5.1-1993.
Note: Stresses above those listed here may cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Maximum ratings are absolute ratings; exceeding only one of these values may cause irreversible damage to the integrated circuit.
Preliminary Data Sheet
147
2001-11-16
PEF 20451 / 20471 / 24471
PRELIMINARY Electrical Characteristics
8.2
Table 38 Parameter
Operating Range Operating Range
Symbol Limit Values min. max. 85 C 3.47 V 5.25 V 0V 5.5 V - 40 3.13 4.75 0 0 0 0 Unit
Operating temperature Supply voltage I/O Supply voltage Ground Voltage applied to input pins
1) 2)
TA VDD VDD5 VSS VIN
Voltage applied to output or I/O pins outputs enabled VOUT outputs high-Z VOUT Voltage applied to H.1x0 I/O pins in 3,3V signal environment3) outputs enabled VOUT outputs high-Z VOUT
1)
VDD V
5.5 V
0 0
VDD V VDD +0.3 V
If one of the H.1x0 input signals from the HTSI are used a 5 V signal environment the special VDD5 pins must be connected to 5 V as reference voltage to fulfill the operating range. If one of the H.1x0 data ports and I/O signals or PCM16..31(IN/OUT) ports from the HTSI are used in a 5 V signal environment the special VDD5 pins must be connected to 5 V as reference voltage to fulfill the operating range. VDD5 are connected to 3.3 V
2)
3)
Note: In the operating range, the functions given in the circuit description are fulfilled.
Preliminary Data Sheet
148
2001-11-16
PEF 20451 / 20471 / 24471
PRELIMINARY Electrical Characteristics
8.3
Crystal Oscillator
The SWITI requires a 16.384 MHz or 32.768 MHz clock source. To supply this a 16.384 MHz or 32.768 MHz crystal can be connected between the ECLKI and ECLKO pins. Figure 59 shows a possible configuration of crystal with the external capacitors.
SW ITI
ECLKI 1 6 .3 8 4 M H z 32 ppm EC LKO
sw iti_ 0 6 1 .e m f
Figure 59
External Crystal
If a crystal is not used, a 16.384 MHz (32 ppm or less) or a 32.768 MHz (32 ppm) signal must be provided to the ECLKI pin and ECLKO should be left unconnected. Table 39 Parameter Clock external input capacitance External Capacitances for Crystal (Recommendation) Symbol Rec. Values 6.8 8.2 Unit pF pF Notes
CECLKI Clock external output capacitance CECLKO
Preliminary Data Sheet
149
2001-11-16
PEF 20451 / 20471 / 24471
PRELIMINARY Electrical Characteristics
8.4
Table 40 Parameter
DC Characteristics DC Characteristics
Symbol Limit Values min. max. - 0.3 0.8 2.0 0.4 2.4 250 Unit Notes V V V mA
Input low voltage Input high voltage Output low voltage Output high voltage Typical power supply current HTSI Input leakage current
VIL VIH VOL VOH ICC IIL IOZ Vt+ VtVhys
VDD+0.3 V IOL = 6 mA IOL = 24 mA1) IOH = - 2.0 mA IOH = - 24.0 mA2) VDD = 3.3 V, TA = 25 C:
PDC = 16.384 MHz 1
A
VDD = 3.3 V, GND = 0 V;
all other pins are floating; VIN = 0 V
Output leakage current Positive Threshold Negative Threshold Hysterisis (Vt+ - Vt-)
1) 2)
1 1.2 0.6 0.4 2.0 1.6
A
V V V
VDD = 3.3 V, GND = 0 V; VOUT = 0 V
only for CT_C8, CT_FRAME, FR_COMP, C2, C4, C16+, C16-, SCLK, SCLK-D pins only for CT_C8, CT_FRAME, FR_COMP, C2, C4, C16+, C16-, SCLK, SCLK-D pins
Note: The listed characteristics are ensured over the operating range of the integrated circuit. Typical characteristics specify mean values expected over the production spread. If not otherwise specified, typical characteristics apply at TA= 25 C and the given supply voltage.
Preliminary Data Sheet
150
2001-11-16
PEF 20451 / 20471 / 24471
PRELIMINARY Electrical Characteristics
8.5
Table 41 Parameter
Capacitances Input/Output Capacitances
Symbol Limit Values Unit Typ. Notes
ECLKI input capacitance ECLKO output capacitance Input capacitance Output capacitance
CECLKI CECLKO CIN COUT
7 7 5 5
pF pF pF pF
fC = 1 MHz
The pins, which are not under test, are connected to GND
8.6
AC Characteristics
Ambient temperature under bias range, VDD = 3.3 V 5 %. Inputs are driven to 2.4 V for a logical '1' and to 0.4 V for a logical '0'. Timing measurements for the H.1x0 clock and frame lines are made at 2.0 V for a logical '1' and at 0.6 V for a logical '0'. Timing measurements for all other signals are made at 2.0 V for a logical '1' and at 0.8 V for a logical '0'. The AC-testing input/output wave forms are shown below.
2.4 V
2.0 V 0.8 V 0,6 V Test Points
2.0 V 0.8 V 0,6 V
Device Under Test
0.4 V
CL = 50 pF (PCM 150 pF H.1x0 12 pF)
Figure 60
I/O Wave Form for AC-Test
Preliminary Data Sheet
151
2001-11-16
PEF 20451 / 20471 / 24471
PRELIMINARY Package Outlines
9
Package Outlines
P-BGA-217-1 (Plastic Ball Grid Array Package)
Figure 61
Outlines of P-BGA-217-1
Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book "Package Information". SMD = Surface Mounted Device Preliminary Data Sheet 152
Dimensions in mm 2001-11-16
PEF 20451 / 20471 / 24471
PRELIMINARY
A
Analog PLL 32 Analyze Memory 30
B
Bidirectional Switching 26 Boundary Scan 54, 56 Broadcast 7 Broadcast Switching 26
C
Clock Fallback 37, 39 Clock Shift 6 Constant Delay 6, 25
D
Data Rate Adaption 7
E
Error Handling - Switching 30
F
Fallback - Primary Master 39 Fallback - Secondary Master 40 Fallback - Slave 41 Flexible Data Rates 6 Frame Group 53 Framing Group 8
G
General Purpose Clocks 8, 53 GPIO Port 8, 52
I
Initialization Procedure 107 Input/Output Tolerance 8 Interrupt Handling 97 Interrupts Masking 98
L
Local Bus Interface 19, 44
Preliminary Data Sheet
153
2001-11-16
PEF 20451 / 20471 / 24471
PRELIMINARY
M
Master - Slave Combination PCM/H.1x0 36 Message Mode 7 Microprocessor Interface 8, 21, 24, 50 Minimum Delay 6 Multipoint 7 Multipoint Switching 25
P
Parallel Mode 4, 7, 29, 131 Phase Alignment 35
R
Read Access 7, 96 Register Configuration Command Register 1 68 Configuration Command Register 2 74 Configuration Register 89 Connection Command Register 66, 92 Destination Address Register 91 Destination Port Address Register 62 General Input Register 92 General Input Register 1 63 General Input Register 2 65 General Purpose Direction Register 84 General Purpose Interrupt Register 85 General Purpose Mask Register 84 General Purpose Port Input Register 83 General Purpose Port Output Register 84 IDCODE Register 94 Input Time Slot Address Register 61 Interrupt Error Mask Register 1 82 Interrupt Error Mask Register 2 83 Interrupt Error Status Register 93 Interrupt Error Status Register 1 79 Interrupt Error Status Register 2 80 Interrupt Mask Register 1 81 Interrupt Status Register 1 78 Message Value Register 78 Output Time Slot Address Register 62 Source Address Register 91 Source Port Address Register 61
Preliminary Data Sheet
154
2001-11-16
PEF 20451 / 20471 / 24471
PRELIMINARY Sub-Channel Address Register 62 Time Slot Value / Configuration Register 94 Time Slot Value Register 85
S
Stream-to-Stream Switching 7, 27 Sub-Channel Switching 6, 117 Switching Factory 25
W
Write Access 7, 96
Preliminary Data Sheet
155
2001-11-16
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